Display device

A display device comprising:

• a display panel including a plurality of scan signal lines;
• and
• a scan signal line drive circuit configured to drive the plurality of scan signal lines, wherein:
• the scan signal line drive circuit is capable of alternately switching, in one vertical scan period, between a drive period, in which the plurality of scan signal lines is sequentially turned into a selected state, and a non-drive period, in which the plurality of scan signal lines is not driven,
• the display panel further includes a HIGH power supply line and a LOW power supply line,
• the scan signal line drive circuit includes a shift register circuit including a plurality of stages,
• a unit circuit in each of the plurality of stages includes:
• a clock terminal to which a clock signal is inputted,
• a SET terminal to which a SET signal is inputted,
• a RESET terminal to which a RESET signal is inputted,
• an output terminal electrically connected to a corresponding one of the plurality of scan signal lines to output a scan signal,
• a first thin film transistor including a first semiconductor layer, a first gate electrode, a first source electrode, and a first drain electrode, the first gate electrode being electrically connected to an internal node, one of the first source electrode and the first drain electrode being electrically connected to the clock terminal, and another one of the first source electrode and the first drain electrode being electrically connected to the output terminal,
• a second thin film transistor including a second semiconductor layer, a second gate electrode, a second source electrode, and a second drain electrode, the second gate electrode being electrically connected to the SET terminal, and one of the second source electrode and the second drain electrode being electrically connected to the internal node, and
• a third thin film transistor including a third semiconductor layer, a third gate electrode, a third source electrode, and a third drain electrode, the third gate electrode being electrically connected to the RESET terminal, and one of the third source electrode and the third drain electrode being electrically connected to the internal node,
• the second gate electrode of the second thin film transistor is an upper gate electrode disposed above the second semiconductor layer via a gate insulating layer,
• another one of the second source electrode and the second drain electrode of the second thin film transistor is electrically connected to the HIGH power supply line, and
• the second thin film transistor further includes a lower gate electrode disposed below the second semiconductor layer, facing a channel region of the second semiconductor layer across a lower insulating layer, and electrically connected to the LOW power supply line, and
• a control signal is applied to another one of the third source electrode and the third drain electrode of the third thin film transistor, the control signal having a first electrical potential lower than a threshold voltage of the first thin film transistor in the drive period and having a second electrical potential higher than the first electrical potential in at least a part of the non-drive period.