Display substrate and display apparatus

A display substrate, comprising:

• a base substrate, wherein the base substrate comprises a display area and a peripheral area surrounding the display area;
• a plurality of pixel units are arranged in an array in the display area;
• a driving module is arranged in the peripheral area;
• and the driving module is configured to provide electrical signals for the plurality of pixel units, to control the plurality of pixel units to operate;
• the driving module comprises a plurality of driving circuits;
• each driving circuit is provided with a corresponding operating signal line group in the peripheral area;
• the operating signal line group comprises at least two operating signal lines, which are connected to the corresponding driving circuit, to provide electrical signals to the corresponding driving circuit;
• the at least two operating signal lines comprise a first clock signal line and a second clock signal line;
• the first clock signal lines for at least two of the plurality of driving circuits are a same first clock signal line;
• and/or
• the second clock signal lines provided for the at least two of the plurality of driving circuits are a same second clock signal line;
• and
• wherein all the pixel units are divided into a plurality of pixel unit groups, each of which is provided with a first driving line, a second driving line, and a third driving line corresponding to the pixel unit group to be connected to each pixel unit in the pixel unit group;
• the plurality of driving circuits comprise:
• a first driving circuit connected to a corresponding first driving line to provide a first driving signal to each pixel unit of the plurality of pixel units of the pixel unit group through the corresponding first driving line, a second driving circuit connected to a corresponding second driving line to provide a second driving signal to the same pixel unit through the corresponding second driving line, and a third driving circuit connected to a corresponding third driving line to provide a third driving signal to the same pixel unit through the corresponding third driving line;
• and
• first clock signal lines for at least two of the first driving circuit, the second driving circuit and the third driving circuit are a same first clock signal line and/or second clock signal lines for at least two of the first driving circuit, the second driving circuit and the third driving circuit are a same second clock signal line;
• wherein the first driving circuit, the second driving circuit, and the third driving circuit corresponding to the same pixel unit are sequentially arranged in a direction away from the display area along a first direction;
• and
• wherein the first clock signal lines for the second driving circuit and the third driving circuit are a same first clock signal line, and the second clock signal lines for the second driving circuit and the third driving circuit are a same second clock signal line;
• and the first clock signal line for the first driving circuit and the first clock signal line for the second driving circuit are two different first clock signal lines, and the second clock signal line for the first driving circuit and the second clock signal line for the second driving circuit are two different second clock signal lines;
• each of the plurality of pixel units comprises a pixel circuit and a light emitting device, and the pixel circuit comprises a writing and compensating circuit and a driving transistor;
• the writing and compensating circuit is configured to write a data compensation voltage to a control electrode of the driving transistor;
• a second electrode of the driving transistor is connected to a first terminal of the light emitting device, the driving transistor is configured to output a corresponding driving current in response to control of the date compensation voltage, and a second terminal of the light emitting device is connected to a first operating voltage terminal;
• the writing and compensating circuit comprises a fifth transistor;
• a control electrode of the fifth transistor is connected to a corresponding second driving line, a first electrode of the fifth transistor is connected to a control electrode of the driving transistor, and a second electrode of the fifth transistor is connected to a second electrode of the driving transistor;
• and
• the fifth transistor is an N-type transistor;
• wherein the pixel unit is provided with a corresponding data line, and the writing and compensating circuit further comprises a third transistor;
• a control electrode of the third transistor is connected to the corresponding first driving line, a first electrode of the third transistor is connected to the data line, and a second electrode of the third transistor is connected to the first electrode of the driving transistor;
• and
• the third transistor is a P-type transistor,
• wherein each pixel unit group is further provided with a corresponding first reset signal line;
• the pixel unit further comprises:
• a first reset circuit;
• the first reset circuit is connected to a first reset power supply terminal, the control electrode of the driving transistor and the corresponding first reset signal line, and is configured to write a first reset voltage provided by the first reset power supply terminal to the control electrode of the driving transistor in response to control of the first reset signal line;
• the writing and compensating circuit is connected to a second operating voltage terminal, the control electrode of the driving transistor, a first electrode of the driving transistor, the corresponding data line, the corresponding first driving line, the corresponding second driving line, and the corresponding third driving line, and the writing and compensating circuit is configured to write the data compensation voltage to the control electrode of the driving transistor in response to control of the first driving line and the second driving line, wherein the data compensation voltage is equal to a sum of a data voltage provided by the data line and a threshold voltage of the driving transistor, wherein the first reset circuit comprises a first transistor, and the writing and compensating circuit further comprises a fourth transistor and a seventh transistor;
• a control electrode of the first transistor is connected to the first reset signal line, a first electrode of the first transistor is connected to the first reset power supply terminal, and a second electrode of the first transistor is connected to the first electrode of the fifth transistor and a second electrode of the seventh transistor;
• a control electrode of the fourth transistor is connected to the third driving line, a first electrode of the fourth transistor is connected to the second operating voltage terminal, and a second electrode of the fourth transistor is connected to the first electrode of the driving transistor;
• a control electrode of the seventh transistor is connected to the second driving line, and a first electrode of the seventh transistor is connected to the control electrode of the driving transistor;
• and
• wherein the fourth transistor is a P-type transistor, and the seventh transistor is an N-type transistor.