Pixel circuits and display panels

A pixel circuit comprising:

• a first light-emitting control transistor, one of a source or a drain of the first light-emitting control transistor being electrically connected to a first power supply line;
• a driving transistor, one of a source or a drain of the driving transistor being electrically connected to another of the source or the drain of the first light-emitting control transistor;
• a second light-emitting control transistor, one of a source or a drain of the second light-emitting control transistor being electrically connected to another of the source or the drain of the driving transistor;
• a light-emitting device, an anode of the light-emitting device being electrically connected to another of the source or the drain of the second light-emitting control transistor, and a cathode of the light-emitting device being electrically connected to a second power supply line;
• a first reset transistor, one of a source or a drain of the first reset transistor being electrically connected to the anode of the light-emitting device, another of the source or the drain of the first reset transistor being electrically connected to a first reset line, and a gate of the first reset transistor being electrically connected to a first control line;
• and
• a bias transistor, one of a source or a drain of the bias transistor being electrically connected to the source or the drain of the driving transistor, another of the source or the drain of the bias transistor being electrically connected to a first wiring, and a gate of the bias transistor being electrically connected to a second wiring;
• wherein a number of times the source or drain of the driving transistor is reset in one frame is greater than a number of times the anode of the light-emitting device is reset in the one frame;
• the one frame comprises at least one first period and at least one second period;
• during the at least one first period, both the first reset transistor and the bias transistor are turned on;
• and during the at least one second period, the first reset transistor is turned off, and the bias transistor is turned on;
• wherein in a condition that the bias transistor is a second reset transistor, the one frame comprises a writing frame and a holding frame, a number of times the second reset transistor is turned on in the writing frame is greater than a number of times the first reset transistor is turned on in the writing frame, and a number of times the second reset transistor is turned on in the holding frame is greater than a number of times the first reset transistor is turned on in the holding frame.