Driving circuitry, driving method, display substrate and display device

A driving method for a driving circuitry,

• wherein a display period comprises a first phase, a second phase and a third phase arranged one after another;
• wherein the driving circuitry comprises a driving output circuitry, a first resetting circuitry and a first isolation circuitry, wherein
• the driving output circuitry is electrically coupled to a first node and a driving signal output end, electrically coupled to a first voltage line or a first clock signal line, and configured to control the driving signal output end to be electrically coupled to the first voltage line or the first clock signal line under the control of a potential at the first node;
• the first resetting circuitry is electrically coupled to a first resetting line, the first clock signal line and a first control node, and configured to control the first clock signal line to write a first clock signal into the first control node under the control of a first resetting signal from the first resetting line;
• and
• the first isolation circuitry is electrically coupled to a second clock signal line, the first control node and the first node, and configured to control the first control node to be electrically coupled to the first node under the control of a second clock signal from the second clock signal line;
• wherein the cascading output circuitry is electrically coupled to the first node, a carry output end and the first voltage line, and configured to control the carry output end to be electrically coupled to the first voltage line under the control of the potential at the first node, and the cascading resetting circuitry is electrically coupled to a second node, the carry output end and a second voltage line, and configured to control the carry output end to be electrically coupled to the second voltage line under the control of a potential at the second node;
• wherein the cascading resetting circuitry comprises a second transistor and a third transistor;
• a gate electrode of the second transistor is electrically coupled to the second node, a first electrode of the second transistor is electrically coupled to the carry output end, and a second electrode of the second transistor is electrically coupled to a fourth node;
• and
• a gate electrode of the third transistor is electrically coupled to the second node, a first electrode of the third transistor is electrically coupled to the fourth node, and a second electrode of the third transistor is electrically coupled to the second voltage line,
• the driving method comprising:
• within the first phase, controlling, by the first resetting circuitry, the first clock signal line to write the first clock signal into the first control node under the control of the first resetting signal from the first resetting line, and when the second clock signal line provides a high voltage signal, controlling, by the first isolation circuitry, the first control node to be electrically coupled to the first node under the control of the second clock signal from the second clock signal line;
• within the second phase, when the second clock signal line provides a high voltage signal, controlling, by the first isolation circuitry, the first control node to be electrically coupled to the first node under the control of the second clock signal, and controlling, by the driving output circuitry, the driving signal output end to be electrically coupled to the first voltage line under the control of the potential at the first node;
• and
• within the third phase, when the second clock signal line provides a high voltage signal, controlling, by the first isolation circuitry, the first control node to be electrically coupled to the first node under the control of the second clock signal.

A driving circuitry, comprising a driving output circuitry, a first resetting circuitry, a first isolation circuitry and a second control node control circuitry,

• wherein the driving output circuitry is electrically coupled to a first node and a driving signal output end, electrically coupled to a first voltage line or a first clock signal line, and configured to control the driving signal output end to be electrically coupled to the first voltage line or the first clock signal line under the control of a potential at the first node;
• the first resetting circuitry is electrically coupled to a first resetting line, the first clock signal line and a first control node, and configured to control the first clock signal line to write a first clock signal into the first control node under the control of a first resetting signal from the first resetting line;
• and
• the first isolation circuitry is electrically coupled to a second clock signal line, the first control node and the first node, and configured to control the first control node to be electrically coupled to the first node under the control of a second clock signal from the second clock signal line,
• wherein the second control node control circuitry is coupled to the first clock signal line, the first voltage line, a second control node, a third node and the second clock signal line, and configured to control the second control node to be electrically coupled to the first voltage line under the control of the first clock signal, and control the third node to be electrically coupled to the second clock signal line under the control of a potential at the second control node,
• wherein the second control node control circuitry is further configured to control the potential at the second control node in accordance with a potential at the third node,
• wherein the second control node control circuitry is further electrically coupled to the input line, and configured to write the first clock signal into the second control node under the control of an input signal from the input line,
• wherein the second control node control circuitry comprises a seventh transistor and an eighth transistor;
• a gate electrode of the seventh transistor is electrically coupled to the input line, a first electrode of the seventh transistor is electrically coupled to the first clock signal line, and a second electrode of the seventh transistor is electrically coupled to a first electrode of the eighth transistor;
• and
• a gate electrode of the eighth transistor is electrically coupled to the input line, and a second electrode of the eighth transistor is electrically coupled to the second control node.