US 12,591,945 B1Granted

System with Voronoi feature transform computation circuitry

AssigneeApple Inc.

InventorsJinsu Lee, Angie Wang

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Abstract

A system or a system-on-a-chip is provided that includes a memory device and a hardware acceleration circuit separate from the memory device and coupled to the memory device via one or more communications paths. The hardware acceleration circuit can include a first processor configured to receive data from the memory device and to process one or more rows of data iteratively or in parallel, an internal memory circuit configured to receive and store processed data output from the first processor, a second processor configured to retrieve the stored data from the internal memory circuit and to process one or more columns of the retrieved data iteratively or in parallel, and a third processor configured to retrieve three-dimensional (3D) data from the memory device and to process one or more stacks of the retrieved 3D data iteratively or in parallel.

Claims17

Dependent claims

A system comprising:

external memory;
and
a hardware acceleration circuit coupled to the external memory via one or more communications paths, the hardware acceleration circuit comprising:
a first processor configured to receive one-dimensional (1D) data, two-dimensional (2D) data, or multiple planes of 2D data from the external memory via the one or more communications paths and to process rows of data in the 1D data, the 2D data, or the multiple planes of 2D data iteratively or in parallel;
an internal memory circuit configured to receive and store processed data output from the first processor;
a second processor configured to retrieve the stored data from the internal memory circuit and to process columns of data in the retrieved data iteratively or in parallel, wherein the external memory is configured to receive processed data output from the second processor via the one or more communications paths;
and
a third processor configured to retrieve three-dimensional (3D) data, including the processed data output by the second processor, from the external memory via the one or more communications paths and to process stacks of data in the 3D data iteratively or in parallel.

5 more elements

A method of operating a system that includes a hardware acceleration circuit coupled to external memory, the method comprising:

reading out one-dimensional (1D) data, two-dimensional (2D) data, or multiple planes of 2D data from the external memory;
with a first processor in the hardware acceleration circuit, processing rows of pixels in the 1D data, the 2D data, or the multiple planes of 2D data iteratively or in parallel and outputting corresponding first processed data;
storing the first processed data on an internal memory circuit in the hardware acceleration circuit or on the external memory;
reading out the stored data from the internal memory circuit or the external memory:
with a second processor in the hardware acceleration circuit, processing columns of pixels in the data read out from the internal memory circuit or the external memory iteratively or in parallel and outputting corresponding second processed data;
and
writing the second processed data into the internal memory circuit or the external memory;
and
with a third processor in the hardware acceleration circuit, reading out third-dimensional (3D) data, including the second processed data, from the external memory or the internal memory circuit and processing stacks of pixels in the 3D data iteratively or in parallel and outputting corresponding third processed data.

6 more elements

Dependencies are inferred from the claim text.