Deep learning acceleration with mixed precision

A method, comprising:

• receiving, at a multiply-accumulate (MAC) component, a map data segment via a first port;
• receiving, at the MAC component, a kernel data segment via a second port;
• receiving, at the MAC component and via a third port, an indication of an input precision mode that indicates a word length for the map data segment and for the kernel data segment;
• generating, by a mixed precision multiplier of the MAC component, a multiplier component output based on the input precision mode and based on:
• multiplying a first half of the map data segment and a first half of the kernel data segment to generate a first multiplier output, and
• multiplying a second half of the map data segment and a second half of the kernel data segment to generate a second multiplier output;
• generating, by a mixed precision adder of the MAC component, an adder component output based on the input precision mode and based on:
• obtaining the multiplier component output from the mixed precision multiplier;
• adding a first half of the multiplier component output and a first half of a return value, received via a return port of the mixed precision adder, to generate a first adder output, and
• adding a second half of the multiplier component output and a second half of the return value to generate a second adder output;
• selecting, by a multiplexer, the adder component output based on the input precision mode;
• and
• outputting the adder component output via a fourth port.

An apparatus, comprising:

• means for receiving a map data segment;
• means for receiving a kernel data segment;
• means for receiving an indication of an input precision mode that indicates a word length for the map data segment and for the kernel data segment;
• means for multiplying a first half of the map data segment and a first half of the kernel data segment to generate a first multiplier output;
• means for multiplying a second half of the map data segment and a second half of the kernel data segment to generate a second multiplier output;
• means for generating a multiplier component output based on the input precision mode, the first multiplier output, and the second multiplier output;
• means for obtaining the multiplier component output;
• means for adding a first half of the multiplier component output and a first half of a return value, received via a return port, to generate a first adder output;
• means for adding a second half of the multiplier component output and a second half of the return value to generate a second adder output;
• means for generating an adder component output based on the input precision mode, the first adder output, and the second adder output;
• means for selecting the adder component output based on the input precision mode;
• and
• means for outputting the adder component output.