Neural network acceleration circuit and method

A neural network acceleration circuit, comprising:

• a data storage module configured to store input data required for a neural network computation;
• a data cache module configured to cache the input data required for the neural network computation output by the data storage module;
• a computing module comprising a plurality of computing units, wherein the plurality of computing units is configured to compute the input data required for the neural network computation output by the data cache module to obtain a plurality of groups of output data;
• and
• a delay processing module configured to perform delay processing on the plurality of groups of output data separately and output the plurality of groups of output data subjected to the delay processing at the same time;
• wherein the data storage module comprises a first data storage sub-module and a second data storage sub-module, and the first data storage sub-module comprises a first data storage unit and a first control unit, wherein the first data storage unit is configured to store first input data required for the neural network computation, and the first control unit is configured to send a control signal to the computing module, the second data storage sub-module comprises a second data storage unit and a second control unit, wherein the second data storage unit is configured to store second input data required for the neural network computation and the second control unit is configured to control a read and write operation of the second data storage unit;
• the data cache module comprises a first register unit and a second register unit, wherein the first data storage unit is connected to the first register unit and the second data storage unit is connected to the second register unit;
• the first register unit comprises n first registers successively connected in series, and the second register unit comprises n second registers successively connected in series;
• the computing module comprises n computing units, an i-th computing unit is connected to an i-th first register of the n first registers, and the i-th computing unit is further connected to an i-th second register of the n second registers;
• the i-th first register of the n first registers transmits the first input data to the i-th computing unit, the i-th second register of the n second registers transmits the second input data to the i-th computing unit, and the i-th computing unit computes the first input data and the second input data to obtain an i-th group of output data, wherein i≤n.