Automated synthesis of virtual system-on-chip environments

A system comprising:

• a memory of a computing device storing computer-executable instructions;
• and one or more hardware processors of the computing device coupled to the memory and configured to:
• receiving a configuration file having specifications for a hybrid virtual system-on-chip (SoC) model, wherein the specifications identify (a) one or more hardware circuitry blocks designed as register transfer level (RTL) abstractions that are present in the system-on-chip model;
• (b) one or more hardware circuitry blocks designed as virtual prototype abstractions;
• (c) unit-level testbenches for the one or more hardware circuitry blocks designed as the RTL abstractions;
• (d) place holder variables in the unit-level testbenches;
• and (e) a shared interface among the one or more hardware circuitry blocks designed as RTL abstractions and the one or more hardware circuitry blocks designed as virtual prototype abstractions;
• creating the hybrid virtual SoC model based on the configuration file by instantiating the one or more hardware circuitry blocks designed as RTL abstractions and a stub hardware circuitry block for each of the one or more hardware circuitry blocks designed as virtual prototype abstractions, wherein the RTL abstracted hardware circuitry blocks and each stub hardware circuitry block are connected via the shared interface;
• and
• generating a SoC-level testbench by integrating the unit-level testbenches for the one or more hardware circuitry blocks represented as RTL abstractions, wherein the SoC-level testbench is configured to receive inputs via the shared interface.

A non-transitory computer-readable storage medium having instructions stored therein, wherein the instructions, when executed by a processor, cause the processor to:

• receive a configuration file having specifications for a hybrid virtual system-on-chip (SoC) model, wherein the specifications identify (a) one or more hardware circuitry blocks designed as register transfer level (RTL) abstractions that are present in the system-on-chip model;
• (b) one or more hardware circuitry blocks designed as virtual prototype abstractions;
• (c) unit-level testbenches for the one or more hardware circuitry blocks designed as the RTL abstractions;
• (d) place holder variables in the unit-level testbenches;
• and (e) a shared interface among the one or more hardware circuitry blocks designed as RTL abstractions and the one or more hardware circuitry blocks designed as virtual prototype abstractions;
• create the hybrid virtual SoC model based on the configuration file by instantiating the one or more hardware circuitry blocks designed as RTL abstractions and a stub hardware circuitry block for each of the one or more hardware circuitry blocks designed as virtual prototype abstractions, wherein the RTL abstracted hardware circuitry blocks and each stub hardware circuitry block are connected via the shared interface;
• and
• generate a SoC-level testbench by integrating the unit-level testbenches for the one or more hardware circuitry blocks represented as RTL abstractions, wherein the SoC-level testbench is configured to receive inputs via the shared interface.