Generating RTL for a circuit using DSP blocks

An apparatus, comprising a non-transitory, machine-readable medium including instructions wherein the instructions, when loaded and executed by a processor, configure the processor to:

• receive a software program executable by an information handling system comprising a multiplication statement that multiplies a first number by a second number, the first number having a first data type and a first bit width, and the second number having a second data type and a second bit width, the first data type and the second data type comprising software data types capable of multiplication by target hardware device utilizing hardware DSP blocks;
• determine a number of hardware DSP blocks of the target hardware device for implementing the multiplication statement of the software program based at least on the first bit width of the first number, the second bit width of the second number, a first DSP bit width corresponding to a bit width of a first operand of the number of hardware DSP blocks, and a second DSP bit width corresponding to a bit width of a second operand of the number of hardware DSP blocks, wherein the number of DSP blocks is two or more;
• and
• generate a Hardware Description Language (HDL) description of the multiplication statement wherein the HDL description comprises distinct portions corresponding to each of the two or more number of hardware DSP blocks.

A machine program product, the machine program product comprising a machine readable storage medium having program instructions embodied therewith, the program instructions executable by a computing device to cause the computing device to:

• convert a multiplication statement in a high-level software language into a Hardware Description Language (HDL) for a programmable hardware circuit having a plurality of hardware DSP blocks, the multiplication statement in the high-level software language comprising a first number multiplied by a second number, the first number having a first data type and a first bit width, and the second number having a second data type and a second bit width, the first data type and the second data type comprising software data types capable of multiplication by the programmable hardware circuit utilizing the plurality of hardware DSP blocks;
• wherein, to convert the multiplication statement in the high-level software language into the HDL for the programmable hardware circuit, the program instructions cause the computing device to:
• determine a partial product multiplication corresponding to the multiplication statement in the high-level software language and having two or more partial product statements based at least on the first bit width of the first number, the second bit width of the second number, a first DSP bit width corresponding to a bit width of a first operand of the plurality of hardware DSP blocks, and a second DSP bit width corresponding to a bit width of a second operand of the plurality of hardware DSP blocks;
• and
• generate an HDL description of the multiplication statement in the high-level software language, wherein the HDL description comprises distinct portions corresponding to each of the two or more partial product statements.