Computational memory

A processing device comprising:

• a two-dimensional array of processing elements, each processing element including:
• an arithmetic logic unit to perform an operation;
• an input selector to select input to the processing element from one of its neighboring processing elements;
• an output selector to select output from the processing element to a different one its neighboring processing elements;
• and
• interconnections among the array of processing elements to provide direct communication between each processing element and its neighboring processing elements;
• and
• a controller connected to the array of processing elements, the controller configured to:
• load an input vector into the array of processing elements;
• divide a non-square matrix of coefficients into a plurality of square submatrices of coefficients;
• load each square submatrix of coefficients into the array of processing elements as serialized coefficients;
• control the array of processing elements to perform a computation with each loaded square submatrix of coefficients and the input vector by:
• performing a parallel operation with the serialized coefficients in the array of processing elements and the input vector;
• accumulating a result vector;
• and
• rotating the result vector in the array of processing elements and repeating the performing of the parallel operation and the accumulating until the operation is complete;
• and
• when each of the computations is complete, outputting the result vector.