System and method for securing high-speed intrachip communications
AssigneeAtom Beam Technologies Inc.
InventorsJoshua Cooper, Charles Yeomans, Aliasghar Riahi, Gregory Caltabiano, Mojgan Haddad
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Abstract
A system and method for securing high-speed communications between processing units on computer chips, wherein a training data set is used to find patterns and associated smaller indices, or codewords, which are stored in a reference codebook library, and where reconstruction and deconstruction algorithms are used to encode and decode data as it is received. The codebook and algorithms may be stored in the firmware of a semiconductor which enable reduced resources and cost when transmitting data between or among devices that utilize such semiconductors.
Claims6
A system for securing high-speed intrachip communications, comprising:
- a complex chip comprising at least two processors and a memory for each processor;
- wherein each processor stores a reference data structure in its respective memory, wherein:
- the reference data-structure is generated by using training data to identify input patterns and their associated compressed representations;
- compressed representations within the reference data structure are assigned such that input patterns that occur more frequently are assigned shorter compressed representations based on a combination of:
- an observed frequency of occurrence of input patterns in the training data;
- and
- an estimated frequency of occurrence of input patterns not in the training data;
- the assignment of shorter compressed representations to more frequently-occurring input patterns is dynamically updated based on ongoing analysis of data transmitted between the processors, combining both the observed frequency in the training data and the estimated frequency of input patterns not in the training data, thereby adapting the reference data structure to evolving communication patterns between the processors.
A method for securing high-speed intrachip communications, comprising:
- a complex chip comprising at least two processors and a memory for each processor;
- wherein each processor stores a reference data structure in its respective memory, wherein:
- the reference data-structure is generated by using training data to identify input patterns and their associated compressed representations;
- compressed representations within the reference data structure are assigned such that more frequently-occurring input patterns are assigned shorter compressed representations based on a combination of:
- an observed frequency of occurrence of input patterns in the training data;
- and
- an estimated frequency of occurrence of input patterns not in the training data;
- the assignment of shorter compressed representations to more frequently-occurring input patterns is dynamically updated based on ongoing analysis of data transmitted between the processors, combining both the observed frequency in the training data and the estimated frequency of input patterns not in the training data, thereby adapting the reference data structure to evolving communication patterns between the processors.
Dependencies are inferred from the claim text.