Protocol including timing calibration between memory request and data transfer
AssigneeRambus Inc.
InventorsFrederick A. Ware, Holden Jessup
Life of this patent
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Abstract
The described embodiments provide a system for controlling an integrated circuit memory device by a memory controller. During operation, the system sends a memory-access request from the memory controller to the memory device using a first link. After sending the memory-access request, the memory controller sends to the memory device a command that specifies performing a timing-calibration operation for a second link. The system subsequently transfers data associated with the memory-access request using the second link, wherein the timing-calibration operation occurs between sending the memory-access request and transferring the data associated with the memory-access request.
Claims20
An integrated circuit (IC) memory controller to control operation of an IC memory device comprising a memory array and a memory interface that comprises internal clocking circuitry, the IC memory controller comprising:
- a command interface to transmit, to the IC memory device, a read command and a phase adjustment command, wherein the phase adjustment command specifies a phase adjustment operation, to be performed by the IC memory device, in an intervening time between receipt of the read command by the IC memory device and the IC memory device outputting data accessed in response to receiving the read command, wherein the IC memory device suspends the internal clock circuitry after outputting the data;
- a data interface to receive the data;
- and
- a transmitter to transmit a timing reference signal to the IC memory device, the timing reference signal to time outputting of the data by the IC memory device.
A method of operation in an integrated circuit (IC) memory controller to control operation of an IC memory device comprising a memory array and a memory interface that comprises internal clocking circuitry, the method comprising:
- transmitting, via a command interface, a read command and a phase adjustment command to an IC memory device, wherein the phase adjustment command specifies a phase adjustment operation to be performed by the IC memory device in an intervening time between receipt of the read command by the IC memory device and the IC memory device outputting data accessed in response to the read command;
- receiving the data via a data interface;
- and
- transmitting a timing reference signal to the IC memory device, the timing reference signal to time outputting of the data by the IC memory device.
An integrated circuit (IC) memory controller to control operation of an IC memory device comprising a memory array and a memory interface that comprises internal clocking circuitry, the IC memory controller comprising:
- command interface circuitry to transmit command information to the IC memory device, wherein in response to receiving at least a portion of the command information, the IC memory device enables clock signal propagation from the internal clocking circuitry, wherein the command information specifies:
- (i) a read operation in which data is accessed from the memory array, and
- (ii) a phase adjustment operation to be performed by the IC memory device in an intervening time between receiving the command information and outputting the data accessed from the memory array;
- and
- data interface circuitry to receive the data;
- transmit circuitry to transmit a timing reference signal to the IC memory device, the timing reference signal to time outputting of the data by the IC memory device.
Dependencies are inferred from the claim text.