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US 12,591,528 B2Granted
Quad-channel memory module
AssigneeRambus Inc.
InventorsSteven C. Woo, Dongyun Lee
Life of this patent
Estimating the term…
Abstract
A four-channel memory module includes four independent memory channels and dual channel memory devices. The channels of the dual channel memory are accessed independently. Thus, the four channels for accessing the memory module each access one channel of a first set and a second set of dual channel memory devices on the module. Dual channel data buffer devices are also included on the module. The dual channel data buffer devices also retime data strobe signals for accesses to/from the sets of dual channel memory devices.
Claims20
A memory module, comprising:
- a first plurality of dynamic random access memory (DRAM) devices each having a respective first memory access interface and a second respective memory access interface to operate independently of each other to access one of two respective sets of memory cores in respective ones of the first plurality of DRAM devices where respective sets of memory cores in the respective ones of the first plurality of DRAM devices are non-overlapping sets;
- a first memory access channel interface to communicate data with each of the respective first memory access interfaces;
- a second memory access channel interface to communicate data with each of the respective second memory access interfaces;
- and
- a first plurality of data buffer devices each having a first host side interface, a first device side interface, a second host side interface, and a second device side interface, respective first host side interfaces and respective second host side interfaces each to operate independently of each other, respective first device side interfaces and respective second device side interfaces to each include more data strobe signals than respective first host side interfaces and respective second host side interface, each of the respective first device side interfaces and each of the respective second device side interfaces to communicate with at least two of the first plurality of DRAM devices.
2 more elements
A memory module, comprising:
- a first plurality of dual independent channel dynamic random access memory (DRAM) devices, each comprising a first memory access interface and a second memory access interface that operate independently of each other to access non-overlapping sets of memory cores;
- and
- a first plurality of dual independent channel data buffer devices each to communicate data with the first plurality of dual independent channel DRAM devices, each of the first plurality of dual independent channel data buffer devices to communicate data with a unique two of the first plurality of dual independent channel DRAM devices, wherein each of the first plurality of dual independent channel data buffer devices comprise a first host-side interface and a second host-side interface that operate independently of each other, each of the first plurality of dual independent channel data buffer devices also comprising a first device-side interface and a second device-side interface that include more data strobe signals that a respective corresponding one of the first host-side interface and a second host-side interface, each of the first plurality of dual independent channel data buffer devices to communicate the data with the unique two of the first plurality of dual independent channel DRAM devices using both dual independent channels of the unique two of the first plurality of dual independent channel DRAM devices and corresponding both dual independent channels of the first plurality of dual independent channel data buffer devices.
A memory module, comprising:
- a plurality of dynamic random access memory (DRAM) devices, each of the plurality of DRAM devices comprising a first memory device access interface and a second memory device access interface that each include command, address, and data transfer function that operate independently of the command, address, and data transfer function of the other of the first memory device access interface and the second memory device access interface;
- a plurality of data buffer devices, each of the plurality of data buffer devices comprising a first DRAM device data interface and a second DRAM device data interface;
- respective ones of the first DRAM device data interfaces of the plurality of data buffer devices to communicate data with a respective unique subset of two of the plurality of DRAM devices via respective ones of the first memory device access interface of the respective unique subset of two of the plurality of DRAM devices, the data communicated with the respective unique subset of two of the plurality of DRAM devices via respective ones of the first memory device access interface of the respective unique subset of two of the plurality of DRAM devices to also be communicated via a one of a first memory channel and a second memory channel;
- respective ones of the second DRAM device data interfaces of the plurality of data buffer devices to communicate data with the respective unique subset of two of the plurality of DRAM devices via respective ones of the second memory device access interface of the respective unique subset of two of the plurality of DRAM devices, the data communicated with the respective unique subset of two of the plurality of DRAM devices via respective ones of the second memory device access interface of the respective unique subset of two of the plurality of DRAM devices to also be communicated via a one of a third memory channel and a fourth memory channel;
- and
- the first memory channel, the second memory channel, the third memory channel, and the fourth memory channel each including command, address, and data transfer functions that operate independently of the command, address, and data transfer function of the other of the first memory channel, the second memory channel, the third memory channel, and the fourth memory channel.
3 more elements
Dependencies are inferred from the claim text.