Priority-based cache eviction policy governed by latency critical central processing unit (CPU) cores

An apparatus comprising:

• means for receiving a read request from a first processing core for first data in a level three (L3) cache memory shared with a second processing core, the first processing core having a first operating frequency less than a second operating frequency of the second processing core;
• and
• means for determining, responsive to the L3 cache memory being full, second data or third data stored in the L3 cache memory to evict based on a priority, the priority being based an operating frequency of a processing core for which the second data or the third data is requested,
• wherein the second data is associated with the second processing core and the third data is associated with the first processing core, the second data having a recency that is later than the third data and further comprising means for evicting the third data from the L3 cache memory.

A processor-implemented method performed by at least one processor, the processor implemented method comprising:

• receiving a read request from a first processing core for first data in a level three (L3) cache memory shared with a second processing core, the first processing core having a first operating frequency less than a second operating frequency of the second processing core;
• and
• determining, responsive to the L3 cache memory being full, second data or third data stored in the L3 cache memory to evict based on a priority, the priority being based on an operating frequency of a processing core for which the second data or the third data is requested,
• wherein the second data is associated with the second processing core and the third data is associated with the first processing core, the second data having a recency that is later than the third data and further comprising evicting the third data from the L3 cache memory.