Memory device and operating method thereof
AssigneeNuvoton Technology Corporation
InventorMin-Nan Cheng
Life of this patent
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Abstract
A memory device and an operating method thereof are provided. The memory device includes a memory controller, an address transforming circuit, and a memory array. The memory controller generates a programming address among multiple candidate programming addresses according to an application. The address transforming circuit stores multiple physical address data and multiple mask data. The physical address data respectively correspond to the candidate programming addresses. The address transforming circuit executes a first logical calculation according to the programming address, the physical address data, and the mask data to generate a physical address. The memory controller executes an access operation on the memory array according to the physical address.
Claims18
A memory device, comprising:
- a memory controller, used to generate a programming address among a plurality of candidate programming addresses according to an application;
- an address transforming circuit, coupled to the memory controller and used to store a plurality of physical address data and a plurality of mask data, wherein the physical address data respectively correspond to the candidate programming addresses, and the address transforming circuit is used to execute a first logical calculation according to the programming address, the physical address data, and the mask data to generate a physical address, and to execute a second logical calculation with an ith-stage sub-address transforming circuit according to the programming address to judge whether to execute the first logical calculation with the ith-stage sub-address transforming circuit, and i is a non-negative integer;
- and
- a memory array, coupled to the memory controller and the address transforming circuit, wherein the memory controller is used to execute an access operation on the memory array according to the physical address,
- wherein the address transforming circuit comprises:
- a multi-stage sub-address transforming circuit, wherein the ith-stage sub-address transforming circuit in the multi-stage sub-address transforming circuit is coupled to the memory controller and the memory array,
- wherein the ith-stage sub-address transforming circuit is used to store corresponding programming address data, the corresponding physical address data, and the corresponding mask data, the programming address data respectively correspond to the candidate programming addresses.
An operating method of a memory device, comprising:
- generating a programming address among a plurality of candidate programming addresses through a memory controller according to an application;
- executing a first logical calculation through an address transforming circuit according to the programming address, a plurality of physical address data, and a plurality of mask data to generate a physical address, wherein the address transforming circuit is used to store the physical address data and the mask data, and the physical address data respectively correspond to the candidate programming addresses;
- executing a second logical calculation with an ith-stage sub-address transforming circuit through an address transforming circuit according to the programming address to judge whether to execute the first logical calculation with the ith-stage sub-address transforming circuit, and i is a non-negative integer;
- and
- executing an access operation on a memory array through the memory controller according to the physical address,
- wherein the address transforming circuit comprises:
- a multi-stage sub-address transforming circuit, wherein the ith-stage sub-address transforming circuit in the multi-stage sub-address transforming circuit is coupled to the memory controller and the memory array,
- wherein the ith-stage sub-address transforming circuit is used to store the corresponding physical address data, the corresponding mask data, and corresponding programming address data, the programming address data respectively correspond to the candidate programming addresses.
Dependencies are inferred from the claim text.