Reducing memory power usage in far memory

An apparatus comprising:

• a power control circuit to monitor power state of the apparatus;
• and
• processing circuitry coupled to the power control circuit and to a memory, wherein, upon trigger of a standby entry, the power control circuit triggers the processing circuitry to:
• determine memory utilization and pinned and locked page information in a first memory portion, and
• move at least a portion of the pinned and locked page information to a second memory portion if a first threshold memory utilization has been reached, wherein the first memory portion includes CXL memory, and the second memory portion includes non-volatile memory or dynamic random access memory (DRAM).

A non-transitory computer readable storage medium having a plurality of instructions stored thereon, which, when executed by a processor, cause the processor to perform operations comprising:

• receiving, from a power control circuit, notifications regarding power state of an apparatus associated with the processor;
• and
• responsive to a notification of entry into a standby mode, determining memory utilization and pinned and locked page information in a first memory portion, and
• moving at least a portion of the pinned and locked page information to a second memory portion if a first threshold memory utilization has been reached, wherein the first memory portion comprises Compute Express Link (CXL) memory and the second memory portion comprises dynamic random access memory (DRAM).