US 12,591,509 B2Granted

Reconfigurable partitioning of high bandwidth memory

AssigneeNokia Solutions and Networks Oy

InventorPranjal Kumar Dutta

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Abstract

Various example embodiments of a capability for supporting reconfigurable partitioning of high bandwidth memory (HBM) in a multi-processor computing system are presented. The capability for supporting reconfigurable partitioning of HBM in a multi-processor computing system, where the multi-processor computing system includes a multi-processor system-on-chip (SoC) including a set of processors supporting respective sets of processor memory channels and an HBM interconnected via an HBM bus supporting a set of HBM bus channels, may support dynamic mapping of the processor memory channels of the processors of the multi-processor SoC to the HBM bus channels of the HBM, thereby overcoming various limitations of a static mapping of the processor memory channels of the processors of the multi-processor SoC to the HBM bus channels of the HBM. The dynamic processor-to-HBM channel mappings enable mapping of any of the processor memory channels of the processors of the multi-processor SoC to any of the HBM bus channels of the HBM.

Claims8

Dependent claims

An apparatus, comprising:

at least one processor;
and
at least one memory storing instructions which, when executed by the at least one processor, cause the apparatus at least to:
determine, for a multi-processor system including a processor core and a high bandwidth memory supporting a high bandwidth memory bus having a set of high bandwidth memory bus channels, a number of the high bandwidth memory bus channels to be used by the processor core;
and
configure, based on the number of the high bandwidth memory bus channels to be used by the processor core, the multi-processor system to provide a high bandwidth memory bus segment for the processor core, wherein, to configure the multi-processor system to provide the high bandwidth memory bus segment for the processor core, the instructions, when executed by the at least one processor, cause the apparatus at least to:
determine, from a set of processor memory channels of the processor core based on the number of high bandwidth memory bus channels to be used by the processor core, a set of selected processor memory channels of the processor core;
determine, from the set of high bandwidth memory bus channels, a set of selected high bandwidth memory bus channels selected for the processor core;
and
configure the multi-processor system to support use of the set of selected high bandwidth memory bus channels selected for the processor core by the set of selected processor memory channels of the processor core.

7 more elements

A method, comprising:

determining, for a multi-processor system including a processor core and a high bandwidth memory supporting a high bandwidth memory bus having a set of high bandwidth memory bus channels, a number of the high bandwidth memory bus channels to be used by the processor core;
and
configuring, based on the number of the high bandwidth memory bus channels to be used by the processor core, the multi-processor system to provide a high bandwidth memory bus segment for the processor core, wherein configuring the multi-processor system to provide the high bandwidth memory bus segment for the processor core includes:
determining, from a set of processor memory channels of the processor core based on the number of high bandwidth memory bus channels to be used by the processor core, a set of selected processor memory channels of the processor core;
determining, from the set of high bandwidth memory bus channels, a set of selected high bandwidth memory bus channels selected for the processor core;
and
configuring the multi-processor system to support use of the set of selected high bandwidth memory bus channels selected for the processor core by the set of selected processor memory channels of the processor core.

4 more elements

Dependencies are inferred from the claim text.