Debugging instruction execution errors in a simulated computer system
AssigneeArm Limited
InventorJohn David Haughton
Life of this patent
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AssigneeArm Limited
InventorJohn David Haughton
Estimating the term…
A method to debug instruction execution errors in a simulated computer system is provided. The method includes generating two separate simulations of the same system and causing a code including a set of instructions to execute on the two separate simulations. The computer implemented method further includes performing an efficient trace operation starting from a start instruction to an end instruction of the set of instructions on the two separate simulations. When trace operation is performed, an instruction execution deviation is identified between the code executed in the two separate simulations by comparing checksum values at a reporting frequency, determining that the comparison of the checksum values indicates a mismatch, and using instruction count and the reporting frequency to capture at least one instruction leading up to the instruction execution deviation.
A computer implemented method, comprising:
A non-transitory computer-readable storage medium having instructions stored thereon for a simulated computer system that when executed by a computing system directs the computing system to:
A computer implemented method, comprising:
Dependencies are inferred from the claim text.