# US 12,591,492 B2 · Data processing network for data processing

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,591,492 B2
- Document ID: US12591492B2
- Status: Granted
- Kind: B2
- Application number: 18/701,355
- Filed: 2022-09-28
- Published: 2025-01-02
- Granted: 2026-03-31
- Earliest claimed: 2021-10-18
- Assignees: Robert Bosch GmbH
- Applicants: Robert Bosch GmbH
- Inventors: Raphael Diziol; Michael Poehnl; Stefan Egenter
- Web page: https://patentgrep.com/patent/US12591492B2

## CPC

- G06F 11/1608: {Error detection by comparing the output signals of redundant hardware (G06F11/1629, G06F11/1666 take precedence; error detection or correction in information storage based on relative movement between record carrier and transducer G11B20/18; checking static stores for correct operation G11C29/00; for logic circuits H03K19/003, H03K19/007; for pulse counters or frequency dividers H03K21/40)}
- G06F 11/1641: {where the comparison is not performed by the redundant processing components}
- G06F 11/0739: {in a data processing system embedded in automotive or aircraft systems}
- G06F 11/0772: {Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers}
- G06F 11/0778: {Dumping, i.e. gathering error/state information after a fault for later diagnosis}
- G06F 11/263: Generation of test inputs, e.g. test vectors, patterns or sequences {; with adaptation of the tested hardware for testability with external testers}
- G06F 11/362: Debugging of software
- G06F 11/3698: Environments for analysis, debugging or testing of software
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A data processing network for performing successive data processing steps in a redundant and validated manner. Each step is used to generate output data from input data. Output data from a first data processing step are at least partially simultaneously input data of a further data processing step. At least one first data processing module is provided for performing each data processing step. The data processing network also includes a comparator module. The first data processing modules transmit control parameters of the individual data processing steps to the comparator module. The comparator module is provides a synchronized control parameter which contains control information relating to at least one performed data processing step. The data processing network includes a recording module in which a debug mode can be activated with which debug data containing information on each execution of a data processing step with the data processing network are recorded.

## Claims

### Claim 1

A data processing system comprising:
a first data processing module, wherein the first data processing module is configured to:
perform a sequence of data processing steps that each transforms respective input data to output data; and
generate, for each of the sequence of steps the first data processing module performs, a respective first control parameter indicative of the performance of that respective step;
a second data processing module, wherein the second data processing module is configured to:
perform an identical sequence of data processing steps as the first data processing module using identical input data as the input data used by the first data processing module; and
generate, for each of the sequence of steps the second data processing module performs, a respective second control parameter indicative of the performance of that respective step;
a synchronizer, wherein the synchronizer is configured to:
receive the first control parameters and the second control parameters;
compare the first control parameters with the second control parameters to determine which of (a) the received first control parameters and (b) the received second control parameters are associated with corresponding ones of the steps performed, respectively, by the first and second data processing modules; and
based on results of the comparison, form tuples that each contains, and associates with each other, a respective subset of data from the first control parameters and a respective subset of data from the second control parameters; and
a recording module, wherein the recording module is configured to receive the tuples formed by the synchronizer and, when a debug mode of the data processing system is activate, store the tuples as debug data indicative of a data processing performance, by the first and second data processing modules, during their respective executions of individual steps of the sequence of steps.

### Claim 2 (depends on 1)

The data processing system according to claim 1, wherein the recording module is configured to, when the debug mode is active, record a state of the first data processing module and/or the second data processing module.

### Claim 3 (depends on 1)

The data processing system according to claim 1, wherein the recording module is configured to, when the debug mode is active, record initial input data for each of the data processing steps performed by the first and/or second data processing modules.

### Claim 4 (depends on 1)

The data processing system according to claim 1, wherein priority parameters are assigned to the data processing steps, and the recording module is configured to record information on the execution of the data processing steps according to the assigned priority parameters.

### Claim 5 (depends on 1)

The data processing system according to claim 1, wherein, when the debug mode is active, the data processing system is configured to enter a slowdown mode that slows execution of the data processing steps to a rate at which the recording module can capture the debug data for each of the data processing steps is.

### Claim 6 (depends on 1)

The data processing network system according to claim 1, wherein the first data processing module is implemented using a first hardware component and the second data processing module is implemented using a second hardware component, and the first hardware component and the second hardware component are physically separated from each other.

### Claim 7 (depends on 6)

The data processing system according to claim 6, wherein the first data processing module is not ASIL-D-compliant.

### Claim 8 (depends on 6)

The data processing system according to claim 6, wherein the synchronizer is implemented using a third hardware component that is physically separated from the first hardware component and the second hardware component.

### Claim 9 (depends on 8)

The data processing system according to claim 8, wherein the first data processing module is not ASIL-D-compliant and the third hardware component is ASIL-D-compliant.

### Claim 10 (depends on 1)

The data processing system according to claim 1, wherein:
the synchronizer includes a data memory configured to store the first and second control parameters with associated time information, thereby creating a logical timeline that represents an execution order of the sequence of steps as performed by the first and second data processing modules; and
the recording module is configured to, when the debug mode is active, record the logical timeline with a flowchart of the performed data processing steps.

### Claim 11

A debugging system for analyzing a data processing performance of a data processing system, wherein the data processing system includes (I) a first data processing module, wherein the first data processing module is configured to: (i) perform a sequence of data processing steps that each transforms respective input data to output data; and (ii) generate, for each of the sequence of steps the first data processing module performs, a respective first control parameter indicative of the performance of that respective step; (II) a second data processing module, wherein the second data processing module is configured to: (i) perform an identical sequence of data processing steps as the first data processing module using identical input data as the input data used by the first data processing module; and (ii) generate, for each of the sequence of steps the second data processing module performs, a respective second control parameter indicative of the performance of that respective step; (III) a synchronizer, wherein the synchronizer is configured to: (i) receive the first control parameters and the second control parameters; (ii) compare the first control parameters with the second control parameters to determine which of (a) the received first control parameters and (b) the received second control parameters are associated with corresponding ones of the steps performed, respectively, by the first and second data processing modules; and (iii) based on results of the comparison, form tuples that each contains, and associates with each other, a respective subset of data from the first control parameters and a respective subset of data from the second control parameters; and (IV) a recording module, wherein the recording module is configured to (i) receive the tuples formed by the synchronizer and (ii) when a debug mode of the data processing system is activate, store the tuples as debug data indicative of a data processing performance, by the first and second data processing modules, during their respective executions of individual steps of the sequence of steps, the debugging system comprising:
debugging data processing modules configured to replicate the sequence of data processing steps performed by the first and second data processing modules of the data processing system;
an import module configured to import the debug data stored by the recording module of the data processing system; and
a processor arrangement that includes at least one processor, wherein the processor arrangement is configured to initiate the replicated data processing based on with the imported debug data.

### Claim 12 (depends on 11)

The debugging system according to claim 11, wherein, during the replicated data processing performed by the debugging data processing modules, a debug comparison is performed between (i) synthetic input data generated by the debugging system and input data that was recorded by the recording module while the debug mode was active.

### Claim 13 (depends on 11)

The debugging system according to claim 11, wherein:
the debugging data processing modules include a first debugging data processing module and a second debugging data processing module, which are respectively configured to replicate the sequence of data processing steps performed by the first data processing module and the second data processing module of the data processing system; and
when the replicated data processing is initiated by the processor arrangement, the import module is further configured to import, into the first and second debugging data processing modules, (i) initial input data for at least one of the sequence of data processing steps and (ii) a state of at least one of the first data processing module and the second data processing module.