Semiconductor device and link configuring method
AssigneeSamsung Electronics Co., Ltd.
InventorsJaeho Cho, Sunho Ki, Wangseok Lee
Life of this patent
Estimating the term…
Abstract
Provided is a semiconductor device that includes a plurality of ports and a PCIe controller. The PCIe controller includes: a link training and status state machine (LTSSM) configured to perform a link-up by configuring a plurality of lanes on the plurality of ports, and a memory storing a first preset as a reference value, the first preset being configured based on a successful link-up performed by the LTSSM. The PCIe controller is configured to perform a verification of a second preset that is configured by the LTSSM based on the reference value, to determine whether the second preset is valid.
Claims16
A semiconductor device comprising:
- a plurality of ports configured to send and receive data on a peripheral component interconnect express (PCIe) interface;
- and
- a PCIe controller operatively connected to the plurality of ports, the PCIe controller comprising:
- a link training and status state machine (LTSSM) configured to perform a link-up by configuring a plurality of lanes on the plurality of ports, and
- a memory configured to store a first preset as a reference value and a first order of states as a first reference order, the first preset being configured based on a successful link-up performed by the LTSSM, and the first order of states corresponding to an order in which the LTSSM operates to execute the successful link-up,
- wherein the PCIe controller is configured to determine whether a second preset configured by the LTSSM is valid, by performing a verification of the second preset based on a comparison of the second preset with the reference value during a link-up process, and based on a comparison of a second order of states with the first reference order, and
- wherein the second order of states corresponds to an order in which the LTSSM operates to execute the link-up process in which the second preset is configured.
A semiconductor device comprising:
- a plurality of ports configured to send and receive data on a peripheral component interconnect express (PCIe) interface;
- and
- a PCIe controller operatively connected to the plurality of ports, wherein the PCIe controller is configured to:
- perform a link-up process to configure a plurality of lanes in on the plurality of ports,
- perform a first verification of a first preset that is configured at a first time during the link-up process, and
- perform a second verification of a second preset that is configured at a second time during the link-up process, after the first time,
- wherein the first verification includes a first comparison of the first preset and a reference preset, and includes a second comparison of a first order of states in which the LTSSM operates in the link-up process before the first time and a reference order of states in which the LTSSM operates to execute a successful link-up,
- wherein the second verification includes a third comparison of the first preset and the reference preset, and includes a fourth comparison of a third order of states in which the LTSSM operates in the link-up process between the first and second times and the reference order of states, and
- wherein the PCIe controller is configured to perform the first and second comparisons based on a first recovery policy, and perform the third and fourth comparisons based on a second recovery policy.
A method of configuring a link, the method comprising:
- obtaining a preset history including a plurality of presets, the plurality of presets being sequentially configured in a recovery operation of a link training and status state machine (LTSSM);
- determining whether a final preset among the plurality of presets is valid, based on a first comparison of an order of states in which the LTSSM operates in the recovery operation and a reference order of states in which the LTSSM operates to execute a successful link-up, and based on a second comparison of the preset history and a reference history corresponding to the successful link-up;
- and
- adjusting a physical layer (PHY) parameter based on determining that the final preset is invalid.
Dependencies are inferred from the claim text.