Technique for sharing context among multiple threads
AssigneeNVIDIA Corporation
InventorsKyrylo Perelygin, Cory Perry, Ze Long
Life of this patent
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Abstract
Apparatuses, systems, and techniques to execute programs in a single hardware context on a graphics processing unit (GPU). In at least one embodiment, resource management patches expressed in library or executable code are applied to one or more kernels to ensure execution in a shared context on a GPU.
Claims30
A processor comprising:
- one or more circuits to cause a compiler to insert one or more instructions into a first software program to control access to one or more computing resources by a second software program, wherein the one or more instructions, when executed, indicate a priority of execution, the priority of execution usable by one or more schedulers of a graphics processing unit (GPU) to execute the first software program and the second software program.
A system, comprising memory to store instructions that, as a result of execution by one or more processors, cause the system to:
- insert one or more instructions into a first software program by a compiler to modify the first software program to control access to one or more computing resources by a second software program, wherein the one or more instructions are to set a priority value indicative of a priority for one or more execution units of a parallel processing unit (PPU) to perform the first software program and the second software program.
A machine-readable medium having stored thereon a set of instructions, which if performed by one or more processors, cause the one or more processors to at least:
- insert one or more instructions into a first software program by a compiler to control access to one or more computing resources by a second software program, wherein the one or more instructions, when executed, set a priority value indicating a priority for one or more execution units of a parallel processing unit (PPU) to perform the first software program and the second software program.
A machine-readable medium having stored thereon a set of executable instructions that when executed by one or more processors of a computer system, cause the computer system to at least:
- insert one or more instructions into a first software program by a compiler to control access to one or more computing resources by a second software program;
- and
- set a priority value indicating an order for one or more execution units of a parallel processing unit (PPU) to perform the first software program and the second software program;
- and
- cause one or more execution units of the parallel processing unit (PPU) to lock one or more memory regions to be usable by the first software program or the second software program.
A method comprising:
- inserting one or more instructions into a first software program by a compiler to control access to one or more computing resources by a second software program, wherein the one or more instructions are to be performed to indicate a priority of execution usable by one or more schedulers of a graphics processing unit (GPU) to execute the first software program and the second software program.
One or more processors, comprising:
- circuitry to cause a compiler to insert one or more instructions into a first software program to control access to one or more computing resources by a second software program, wherein the one or more instructions, when executed, indicate an order of execution usable by one or more schedulers to execute the first software program and the second software program, wherein the one or more instructions, if executed, cause a context to be shared by the first software program and the second software program, the context comprising a shared memory and one or more execution units of a parallel processing unit (PPU).
One or more processors, comprising:
- circuitry to cause a compiler to insert one or more instructions into a first software program to control access to one or more computing resources by a second software program, wherein the one or more instructions, when executed, indicate an order of execution usable by one or more schedulers to execute the first software program and the second software program, wherein the one or more instructions, if executed, cause one or more execution units of a parallel processing unit (PPU) to stop execution of the first software program by the one or more execution units and start execution of the second software program by the one or more execution units.
Dependencies are inferred from the claim text.