Adaptive scheduling with dynamic partition-load balancing for fast partition compilation

A system comprising:

• a memory;
• and
• at least one processor coupled to the memory and configured to perform operations comprising:
• compiling, by an electronic design automation (EDA) process via a plurality of computing elements, at least one partition of a plurality of partitions of a design specification of an integrated circuit, each partition of the plurality of partitions comprising one or more circuit blocks;
• training a machine learning model during compilation of the design specification of the integrated circuit to compute an estimated hardware-resource amount based on a plurality of features of the at least one partition of the plurality of partitions and an actual hardware-resource amount to compile the at least one partition of the plurality of partitions of the design specification of the integrated circuit;
• determining an estimate of a hardware-resource amount to be used by the EDA process to compile remaining partitions of the plurality of partitions comprising supplying a plurality of features of a partition of the remaining partitions of the design specification of the integrated circuit to the machine learning model, the partition of the remaining partitions being different from the at least one partition of the plurality of partitions used in training the machine learning model, the plurality of features comprising a number of syntactic blocks specifying the one or more circuit blocks of the partition of the remaining partitions;
• determining the estimate of the hardware-resource amount is within an available hardware resource amount among the plurality of computing elements, wherein the available hardware resource amount of computing elements are available for parallel use by the EDA process;
• and
• compiling the remaining partitions of the design specification of the integrated circuit by a specified number of computing elements, the specified number of computing elements being computed to match the estimate of the hardware-resource amount to be used by the EDA process to compile the remaining partitions of the plurality of partitions, the specified number being computed based at least in part on a number of the remaining partitions.

A non-transitory computer-readable storage medium storing instructions that, when executed by at least one processor, cause the at least one processor to perform operations comprising:

• compiling, by an electronic design automation (EDA) process via a plurality of computing elements having a first memory allocation, at least one partition of a plurality of partitions of a design specification of an integrated circuit, each partition of the plurality of partitions comprising one or more circuit blocks;
• training a machine learning model during compilation of the design specification of the integrated circuit to compute an estimated hardware-resource amount based on a plurality of features of the at least one partition of the plurality of partitions and an actual hardware-resource amount to compile the at least one partition of the plurality of partitions of the design specification of the integrated circuit;
• determining an estimate of a hardware-resource amount to be used by the EDA process to compile remaining partitions of the plurality of partitions, comprising supplying a plurality of features of a partition of the remaining partitions of the design specification of the integrated circuit to the machine learning model, the partition of the remaining partitions being different from the at least one partition of the plurality of partitions used in training the machine learning model, the plurality of features comprising a number of syntactic blocks specifying the one or more circuit blocks of the partition of the remaining partitions;
• determining the estimate of the hardware-resource amount is within an available hardware resource amount among the plurality of computing elements, wherein the available hardware resource amount of computing elements are available for parallel use by the EDA process;
• and
• compiling the remaining partitions of the design specification of the integrated circuit by the EDA process via a specified number of computing elements of the plurality of computing elements having a second memory allocation, the specified number of computing elements or the second memory allocation being computed to match the estimate of the hardware-resource amount to be used by the EDA process to compile the remaining partitions of the plurality of partitions, the specified number of computing elements or the second memory allocation being computed based at least in part on a number of the remaining partitions.