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US 12,591,434 B2Granted
Shadow cache for securing conditional speculative instruction execution
OwnerSteven Jeffrey Wallachinventor
Life of this patent
Estimating the term…
Abstract
A computing device, having: a processor; memory; a first cache coupled between the memory and the processor; and a second cache coupled between the memory and the processor. During speculative execution of one or more instructions, effects of the speculative execution are contained within the second cache.
Claims20
A computing device, comprising:
- a processor;
- a first cache;
- and
- a second cache;
- wherein the processor is configured to:
- determine presence of two branches of second instructions following a first branch instruction, the two branches including a first branch and a second branch;
- execute the first branch using the first cache;
- and
- execute the second branch using the second cache.
6 more elements
A method, comprising:
- coupling a cache system between a processor and a memory;
- and
- coupling a shadow cache between the processor and the memory in parallel with the cache system, wherein a location in the memory is accessible to the processor via both the cache system and the shadow cache.
A system, comprising:
- a cache system configured between a processor and a memory;
- and
- a shadow cache configured between the processor and the memory in parallel with the cache system, wherein a location in the memory is accessible to the processor via both the cache system and the shadow cache.
Dependencies are inferred from the claim text.