Artificial intelligence processing apparatus, and data prefetching device and method for artificial intelligence processor

A prefetching device for an artificial intelligence processor, comprising:

• at least one control and status register configured to prefetch data, stored in an external off-chip memory, into an internal on-chip memory in an artificial intelligence processor, and to store information including an address value and a total amount of matrix operation data;
• a matrix operation discrimination unit configured to, as a kernel program is executed, extract a matrix operation instruction among instructions provided from an instruction cache of the off-chip memory;
• a prefetching/non-prefetching determination unit configured to determine whether prefetching is enabled based on a result of extracting the matrix operation instruction;
• a prefetch block number determination unit configured to, as prefetching is enabled, determine a number of blocks to be prefetched based on the information stored in the at least one control and status register;
• and
• a request signal generation unit configured to determine a bus burst value corresponding to the determined number of blocks and transmit the bus burst value as a data request signal through a bus interface.

A prefetching method for an artificial intelligence processor, comprising:

• prefetching data, stored in an external off-chip memory, into an internal on-chip memory in the artificial intelligence processor, and storing information including an address value and a total amount of matrix operation data in at least one control and status register;
• as a kernel program is executed, extracting a matrix operation instruction among instructions provided from an instruction cache of the off-chip memory;
• determining whether prefetching is enabled based on a result of extracting the matrix operation instruction;
• as prefetching is enabled, determining a number of blocks to be prefetched based on the information stored in the at least one control and status register;
• and
• determining a bus burst value corresponding to the determined number of blocks and transmitting the bus burst value as a data request signal through a bus interface.