Memory interface

A computing device, comprising:

• a processor;
• a memory;
• an address decoder connected between the processor and the memory, and configured to receive a memory address from the processor, decode the memory address, and output an address command to the memory;
• an instruction decoder connected between the processor and the memory, and configured to receive an instruction from the processor, decode the instruction, and output a command to the memory, the instruction decoder further configured to output a plurality of control codes based on the received instruction;
• and
• an execution circuit including a logic circuit, a data output terminal connected to the processor, a write data input terminal configured to receive input data, and a read data input terminal configured to receive data retrieved from the memory based on the address command, wherein the execution circuit is configured to provide one of an arithmetic result or the data retrieved from the memory at the data output terminal based on the plurality of control codes;
• wherein the plurality of control codes includes a read control code, and the execution circuit includes a read multiplexer (MUX) having a first input terminal connected to the read data input terminal, a second input terminal connected to receive the arithmetic result, a control terminal connected to receive the read control code, and the data output terminal, wherein the read MUX is configured to output the one of the retrieved data or the arithmetic result in response to the read control code;
• wherein the logic circuit includes:
• a first data input terminal;
• a second data input terminal;
• a control terminal, wherein the plurality of control codes includes a command code received by the control terminal of the logic circuit;
• and
• an output terminal configured to provide the generated arithmetic result;
• and
• wherein the execution circuit includes:
• a first register having an output terminal connected to the first data input terminal of the logic circuit;
• and
• a second register having an output terminal connected to the second data input terminal of the logic circuit;
• a first input data MUX having an output terminal connected to an input terminal of the first register;
• a second input data MUX having an output terminal connected to an input terminal of the second register;
• wherein the first input data MUX and the second input data MUX each include:
• a first input terminal connected to the write data input terminal;
• a second input terminal connected to the output terminal of the logic circuit;
• a third input terminal connected to the read data input terminal;
• a fourth input terminal, wherein the fourth input terminal of the first input data MUX is connected to the output terminal of the first register, and the fourth input terminal of the second input data MUX is connected to the output terminal of the second register;
• and
• a control terminal, wherein the plurality of control codes includes a first data select code received by the control terminal of the first input data MUX, and a second data select code received by the control terminal of the second input data MUX.

A method, comprising:

• receiving an instruction from a processor by an instruction decoder;
• outputting a memory address command based on the instruction to a memory by the instruction decoder;
• outputting a control code to an execution circuit connected to the memory, wherein the control code includes a read control code;
• receiving data read from the memory by the execution circuit based on the memory address command;
• generating an arithmetic result by a logic circuit of the execution circuit based on the control code and the data read from the memory;
• and
• outputting the arithmetic result by the logic circuit;
• wherein the execution circuit includes a read multiplexer (MUX) having a first input terminal connected to the read data input terminal, a second input terminal connected to receive the arithmetic result, a control terminal connected to receive the read control code, and the data output terminal, wherein the read MUX is configured to output the one of the retrieved data or the arithmetic result in response to the read control code;
• and
• wherein the logic circuit includes:
• a first data input terminal;
• a second data input terminal;
• a control terminal, wherein the plurality of control codes includes a command code received by the control terminal of the logic circuit;
• and
• an output terminal configured to provide the generated arithmetic result;
• and
• wherein the execution circuit includes:
• a first register having an output terminal connected to the first data input terminal of the logic circuit;
• and
• a second register having an output terminal connected to the second data input terminal of the logic circuit;
• a first input data MUX having an output terminal connected to an input terminal of the first register;
• a second input data MUX having an output terminal connected to an input terminal of the second register;
• wherein the first input data MUX and the second input data MUX each include:
• a first input terminal connected to the write data input terminal;
• a second input terminal connected to the output terminal of the logic circuit;
• a third input terminal connected to the read data input terminal;
• a fourth input terminal, wherein the fourth input terminal of the first input data MUX is connected to the output terminal of the first register, and the fourth input terminal of the second input data MUX is connected to the output terminal of the second register;
• and
• a control terminal, wherein the plurality of control codes includes a first data select code received by the control terminal of the first input data MUX, and a second data select code received by the control terminal of the second input data MUX.