Data processing method for processing unit, electronic device and computer readable storage medium

An electronic device, comprising:

• a systolic array, comprising a plurality of data processing units, wherein each of the data processing units comprises a first source register, a second source register, destination register and a calculation unit including a multiplier and an adder, wherein the systolic array is an implementation of a general matrix multiply arithmetic logic unit;
• a processor;
• and
• a memory coupled to the processor, the memory having instructions stored therein, wherein the processor is configured to execute the instructions to control each of the data processing units to:
• in mth clock cycle, activate a timer to send a first clock control signal to the first source register and the second source register, so that in the mth clock cycle, the first source register inputs a first n-dimensional vector into the calculation unit which is a hardware logic component, and the second source register inputs a second n-dimensional vector into the calculation unit, perform a first dot product operation on the first n-dimensional vector and the second n-dimensional vector by the calculation unit, and determine a first exponent value of a floating point number of a result of the first dot product operation performed, and store the first exponent value, where m is a positive integer greater than or equal to 1;
• in m+1th clock cycle, activate the timer to send a second clock control signal to the first source register and the second source register, so that in the m+1th clock cycle, the first source register inputs a third n-dimensional vector into the calculation unit, and the second source register inputs a fourth n-dimensional vector into the calculation unit, determine n second exponent values in the calculation unit, and store the n second exponent values, the second exponent values being obtained by adding the exponent of a floating point number in one of the third n-dimensional vector and the fourth n-dimensional vector with the exponent of a corresponding floating point number in the other of the two n-dimensional vectors, n being a positive integer greater than or equal to 1;
• determine a maximum value among the first exponent value and the determined n second exponent values;
• use a number of reserved bits of a mantissa of the floating point number stored in a destination register as a first threshold;
• determine whether a target second exponent value exists among the n second exponent values, an absolute value of a difference between the target second exponent value and the maximum value being greater than or equal to the first threshold;
• and
• in response to determining that the target second exponent value exists in n second exponent values, send a signal to the multiplier of the calculation unit to cause the multiplier to bypass a multiply operation of two floating point numbers corresponding to the target second exponent value, during the m+1th clock cycle.