Back to results
US 12,591,381 B2Granted
Method for adjusting operation mode, memory storage device and memory control circuit unit
AssigneePhison Electronics Corp.
InventorsYen Chun Tseng, Shih Hwa Liu
Life of this patent
Estimating the term…
Abstract
A memory control method, a memory storage device and a memory control circuit unit are disclosed. The method includes: detecting a state of the memory storage device; and adjusting an operation mode of the memory storage device according to the state of the memory storage device, wherein the operation mode includes a first operation mode and a second operation mode, and a first waiting time before the memory storage device entering a power saving mode in the first operation mode is longer than a second waiting time before the memory storage device entering the power saving mode in the second operation mode.
Claims18
A memory control method, adapted to a memory storage device, wherein the memory control method comprises:
- detecting a state of the memory storage device;
- updating a reference value based on the state of the memory storage device, wherein the reference value is related to a performance of the memory storage device within a target time range;
- and
- adjusting an operation mode of the memory storage device according to the reference value, comprising:
- in response to the reference value meeting a first trigger condition, setting the operation mode of the memory storage device to the first operation mode;
- and
- in response to the reference value meeting a second trigger condition, setting the operation mode of the memory storage device to the second operation mode,
- wherein the first trigger condition is different from the second trigger condition,
- wherein the operation mode comprises a first operation mode and a second operation mode,
- a first waiting time before the memory storage device entering a power saving mode in the first operation mode is longer than a second waiting time before the memory storage device entering the power saving mode in the second operation mode.
7 more elements
A memory storage device, comprising:
- a connection interface unit, configured to couple to a host system;
- a rewritable non-volatile memory module;
- and
- a memory control circuit unit, coupled to the connection interface unit and the rewritable non-volatile memory module,
- wherein the memory control circuit unit is configured to:
- detect a state of the memory storage device;
- update a reference value based on the state of the memory storage device, wherein the reference value is related to a performance of the memory storage device within a target time range;
- and
- adjust an operation mode of the memory storage device according to the reference value, wherein an operation of the memory control circuit unit adjusting the operation mode of the memory storage device according to the reference value comprises:
- in response to the reference value meeting a first trigger condition, setting the operation mode of the memory storage device to the first operation mode;
- and
- in response to the reference value meeting a second trigger condition, setting the operation mode of the memory storage device to the second operation mode,
- wherein the first trigger condition is different from the second trigger condition,
- wherein the operation mode comprises a first operation mode and a second operation mode,
- a first waiting time before the memory storage device entering a power saving mode in the first operation mode is longer than a second waiting time before the memory storage device entering the power saving mode in the second operation mode.
12 more elements
A memory control circuit unit, configured to control a rewritable non-volatile memory module, wherein the memory control circuit unit comprises:
- a host interface, configured to couple to a host system;
- a memory interface, configured to couple to the rewritable non-volatile memory module;
- and
- a memory management circuit, coupled to the host interface and the memory interface,
- wherein the memory management circuit is configured to:
- detect a state of the memory storage device;
- update a reference value based on the state of the memory storage device, wherein the reference value is related to a performance of the memory storage device within a target time range;
- and
- adjust an operation mode of the memory storage device according to the reference value, wherein an operation of the memory management circuit adjusting the operation mode of the memory storage device according to the reference value comprises:
- in response to the reference value meeting a first trigger condition, setting the operation mode of the memory storage device to the first operation mode;
- and
- in response to the reference value meeting a second trigger condition, setting the operation mode of the memory storage device to the second operation mode,
- wherein the first trigger condition is different from the second trigger condition,
- wherein the operation mode comprises a first operation mode and a second operation mode,
- a first waiting time before the memory storage device entering a power saving mode in the first operation mode is longer than a second waiting time before the memory storage device entering the power saving mode in the second operation mode.
12 more elements
Dependencies are inferred from the claim text.