In-situ memory compression
AssigneeMicron Technology, Inc.
InventorsSaideep Tiku, Poorna Kale
Life of this patent
Estimating the term…
Abstract
The subject application relates to in-situ compression of data in a main memory and storing of the compressed data in the same main memory to improve memory optimization. A hardware logic of a memory device may receive modified pages from a first portion of memory array, cause a page compression accelerator in the hardware logic to compress the received modified pages to generate compressed data, and facilitate storing of the compressed data to a second portion of memory array of the same memory device. By using in-situ data compression, memory optimization in a computing device is improved.
Claims16
A memory module, comprising:
- a volatile random access memory (RAM) array;
- and
- complimentary metal oxide semiconductor (CMOS) logic under the RAM array on the memory module, the CMOS logic including a page compression accelerator (PCA) that is coupled to the volatile RAM array, wherein the CMOS logic is configured to:
- receive data comprising pages marked as dirty pages from a first portion of the RAM array;
- cause the PCA to compress the data to generate compressed data;
- and
- cause the compressed data to be stored in a second portion of the volatile RAM array;
- and
- wherein the memory module is configured to operate as main memory for a computing system.
A memory module, comprising:
- a first volatile random access memory (RAM) array;
- a second volatile RAM array;
- complimentary metal oxide semiconductor (CMOS) logic under the second volatile RAM array on the memory module, the CMOS logic including a page compression accelerator (PCA) that is coupled to the second volatile RAM array;
- and
- a memory controller coupled to the first volatile RAM array and to the second volatile RAM array, wherein the memory controller is configured to move data comprising pages marked as dirty pages from the first volatile RAM array to the second volatile RAM array in response to a memory reclamation command,
- wherein the CMOS logic is configured to:
- cause the PCA to compress the data to generate compressed data;
- and
- cause the compressed data to be stored in the second volatile RAM array;
- and
- wherein the memory module is configured to operate as main memory for a computing system.
A method, comprising:
- receiving, by a complimentary metal oxide semiconductor (CMOS) logic under a volatile random access memory (RAM) array on a memory module, data comprising pages marked as dirty pages from a first portion of the volatile RAM array, wherein the CMOS logic is coupled to the volatile RAM array and includes a page compression accelerator (PCA);
- receiving a command at the CMOS logic;
- executing the command on the PCA to compress the received data to generate a compressed data;
- storing the compressed data to a second portion of the volatile RAM array;
- and
- operating the memory module as main memory for a computing system.
Dependencies are inferred from the claim text.