Memory programming method, memory device, and memory system

A memory device, comprising:

• a plurality of memory cells;
• and
• a peripheral circuit coupled to the plurality of memory cells and configured to:
• in response to a programming temperature of the memory cells being within a first temperature range, perform following operations during a time period in which the programming temperature is within the first temperature range:
• performing a first incremental step pulse programming on the memory cells, a first incremental voltage in the first incremental step pulse programming being less than a default incremental voltage, an initial programming voltage of the first incremental step pulse programming being greater than a default initial programming voltage,
• performing a verification of a first programmed state on the memory cells,
• performing a second incremental step pulse programming on the memory cells, a second incremental voltage in the second incremental step pulse programming being greater than the first incremental voltage and less than the default incremental voltage, and
• performing a verification of a second programmed state on the memory cells, a second threshold voltage of the second programmed state being greater than a first threshold voltage of the first programmed state.

A memory system, comprising:

• a memory device, comprising:
• a plurality of memory cells;
• and
• a peripheral circuit coupled to the plurality of memory cells and configured to:
• in response to a programming temperature of the memory cells being within a first temperature range, perform following operations during a time period in which the programming temperature is within the first temperature range:
• performing a first incremental step pulse programming on the memory cells, a first incremental voltage in the first incremental step pulse programming being less than a default incremental voltage, an initial programming voltage of the first incremental step pulse programming is greater than a default initial programming voltage,
• performing a verification of a first programmed state on the memory cells,
• performing a second incremental step pulse programming on the memory cells, a second incremental voltage in the second incremental step pulse programming being greater than the first incremental voltage and less than the default incremental voltage, and
• performing a verification of a second programmed state on the memory cells, a second threshold voltage of the second programmed state being greater than a first threshold voltage of the first programmed state;
• and
• a memory controller coupled to the memory device and configured to control the memory device through the peripheral circuit.