Performance states in integrated circuit

A method, comprising:

• powering, while an integrated circuit is in a first performance state, a plurality of component circuits of the integrated circuit, wherein the plurality of component circuits is configured to access data from a memory via a memory controller circuit configured to store the data in a memory cache, and wherein a particular component circuit of the plurality of component circuits includes a local memory;
• transitioning the integrated circuit to a second performance state in which the memory cache and the particular component circuit remain powered on while remaining ones of the plurality of component circuits are powered off, and wherein the transitioning includes:
• loading, into the memory cache, data from a memory space allocated in the memory to the particular component circuit, wherein, while the integrated circuit is in the second performance state, the particular component circuit accesses data from the local memory and the memory cache;
• and
• transitioning the memory into a self-refresh mode;
• and
• transitioning the integrated circuit to a third performance state, wherein the transitioning to the third performance state includes:
• power gating a portion of the particular component circuit, wherein, while the integrated circuit is in the third performance state, the particular component circuit accesses data from the local memory;
• and
• transitioning the memory cache into a retention mode.

A non-transitory computer-readable medium having stored thereon design information that specifies a circuit design in a format recognizable by a fabrication system that is configured to use the design information to fabricate a hardware integrated circuit that comprises:

• a plurality of component circuits configured to access data from a memory, wherein a particular component circuit of the plurality of component circuits is configured to remain powered on when remaining ones of the plurality of component circuits are powered off;
• a memory controller circuit that is configured to interface to the memory on behalf of the plurality of component circuits, wherein the memory controller circuit is configured to store data from the memory in a memory cache to service requests from the plurality of component circuits;
• a power management circuit that is configured to transition the hardware integrated circuit between a plurality of different performance states that includes:
• a first performance state in which:
• the memory is in a self-refresh mode;
• the particular component circuit and the memory cache receive power;
• a first processor of the particular component circuit is configured to access data from the memory cache;
• and
• a second processor of the particular component circuit is configured to access data from a local memory of the particular component circuit;
• and
• a second performance state in which:
• the memory is in a self-refresh mode;
• the first processor is power gated and the memory cache is in a retention mode;
• and
• the second processor is configured to access data from the local memory.