US 12,591,292 B2Granted

Processor-based system employing configurable local frequency throttling management to manage power demand and consumption, and related methods

AssigneeMicrosoft Technology Licensing, LLC

InventorsSmitha L. Rapaka, Xiaoling Xu, Venkatesh Balasubramanian, Sunil K Vemula, Derek E. Gladding, Cesar Maldonado

Life of this patent

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Abstract

Processor-based systems employing configurable local frequency throttling management to manage power demand and consumption, and related methods. For example, such processor-based systems may include a processor and other power circuitry to control power to the processor. The processor includes a clock control circuit that is configured generate a clock signal(s) at a designated frequency to clock a processor core(s) in the processor at a desired operating frequency(ies). The clock control circuit is configured to dynamically throttle (i.e., limit and/or reduce) the frequency(ies) of a clock signal(s) clocking the processor in response to a frequency throttle event that may be an unexpected event. Reducing power demand may be important to ensure that the processor can continue to operate under interrupted or reduced power supply conditions. It may be faster to throttle the operating frequency of a processor than to throttle the operating voltage of power supplied to the processor.

Claims19

Dependent claims

A processor-based system, comprising:

a clock control circuit configured to generate a clock signal at a current frequency on a clock output;
a processing unit comprising at least one compute processor core each coupled to the clock output, each configured to execute program code at a rate based on the current frequency of the clock signal as an operating frequency;
a power control circuit configured to control power provided to the processing unit;
and
a throttle frequency memory configured to store a throttle frequency programmed for shutdown of the processing unit;
wherein the clock control circuit is configured to:
receive a frequency throttle signal indicating a thermal shutdown event where a temperature at or surrounding the processing unit is beyond operating capabilities or specifications of the processing unit;
and
in response to receiving the frequency throttle signal indicating the thermal shutdown event:
generate the clock signal at the throttle frequency lower than the current frequency, and
send a frequency throttle completion signal to the power control circuit responsive to the throttle frequency being reached;
and
wherein the power control circuit is configured to:
shutdown operation of the processing unit in response to receiving the frequency throttle completion signal from the clock control circuit to allow the processing unit to cool within the operating capabilities or specifications of the processing unit;
and
reset generation of power to the processing unit for continued operation of the processing unit.

13 more elements

A method of throttling an operating frequency of a processor in a processor-based system, comprising:

generating a clock signal at a current frequency on a clock output;
executing program code at a rate based on the current frequency of the clock signal in a processing unit comprising at least one compute processor core receiving the clock signal;
receiving a frequency throttle signal indicating a thermal shutdown event where a temperature at or surrounding the processing unit is beyond operating capabilities or specifications of the processing unit;
and
in response to receiving the frequency throttle signal indicating the thermal shutdown event, generating the clock signal at a throttle frequency lower than the current frequency and programmed for shutdown of the processing unit, by:
generating the clock signal on the clock output at the throttle frequency lower than the operating frequency;
executing program code at a rate based on the throttle frequency of the clock signal in the processing unit;
shutdown operation of the processing unit in response to the processing unit executing program code at the throttle frequency to allow the processing unit to cool within the operating capabilities or specifications of the processing unit;
and
resetting generation of power to the processing unit for continued operation of the processing unit.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application: 18/382,318Filed 20 Oct 2023 · continuation
Priority: 8 Feb 2021
Published: US 2024/0045489 A18 Feb 2024
Granted: 31 Mar 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification10 codes

G06F 1/324
Power saving characterised by the action undertaken: by lowering clock frequency
G06F 1/06
Generating or distributing clock signals or signals derived directly therefrom: clock generators producing several clock signals
G06F 1/08
Generating or distributing clock signals or signals derived directly therefrom: clock generators with changeable or programmable clock frequency
G06F 1/3296
Power saving characterised by the action undertaken: by lowering the supply or operating voltage

Family

Application17/170,418Parent of this continuation · filed 8 Feb 2021
US 2024/0045489 A1Pre-grant publication · published 8 Feb 2024
US 11,822,414 B2Parent of this continuation
US 2022/0253120 A1Published application
US 12,591,292 B2This patent

From the US filing history. Foreign family members aren’t listed.