Information processing device having sub-processor for data evacuation process

An information processing device, comprising:

• a main processing circuit that is configured to realize various types of processing by executing a program;
• dynamic random-access memory (DRAM) that is volatile memory and that requires refresh processing to retain data;
• static random-access memory (SRAM) that is volatile memory and that does not require refresh processing to retain data;
• and
• a sub-processing circuit of which a processing speed is slower than that of the main processing circuit, the sub-processing circuit being connected between the DRAM and the SRAM, wherein
• the main processing circuit is configured to
• determine whether an execution condition to execute an evacuation process is satisfied, the evacuation process including reading particular data that is data stored in the DRAM and storing the particular data read from the DRAM in the SRAM, and
• transmit an execution signal to the sub-processing circuit in response to a determination that the execution condition is satisfied,
• the sub-processing circuit is configured to
• execute the evacuation process in response to the execution signal transmitted from the main processing circuit, and
• transmit a completion signal to the main processing circuit in response to completion of the evacuation process, and
• the main processing circuit is further configured to
• cut off electric power supply to the DRAM while maintaining electric power supply to the SRAM, in response to receiving the completion signal from the sub-processing circuit,
• restart the electric power supply to the DRAM while maintaining electric power supply to the SRAM, and
• read the particular data stored in the SRAM and store the particular data read from the SRAM in the DRAM, in a case where the particular data is stored in the SRAM at a timing of restarting the electric power supply to the DRAM.