Reset output with open drain configuration for functional safety (FUSA) applications

An integrated circuit (IC), comprising:

• a control circuit defining a reset terminal and configured to determine an error condition in the IC and to generate a reset signal on the reset terminal, based on determining the error condition in the IC;
• a field-effect transistor (FET) defining a drain connected to an output terminal of the IC, and a source connected to a ground terminal of the IC, the FET configured to selectively conduct a first current between the output terminal and the ground terminal to drive the output terminal to a low voltage state, thereby signaling the error condition in the IC;
• an internal pull-up resistor connected between a signal terminal of the IC and a gate of the FET to conduct a second current therebetween and to drive the FET to a conductive state;
• and
• a FET driver circuit connected to the reset terminal of the control circuit and configured to selectively drive the FET to a non-conductive state in response to the reset signal,
• wherein the FET is an N-type metal-oxide-semiconductor (NMOS) device having a threshold voltage that is less than 0 Volts, and
• wherein the FET driver circuit comprises a negative voltage charge pump (NVCP) configured to selectively drive a gate voltage of the FET below the threshold voltage to drive the FET to the non-conductive state in response to the reset signal.

An integrated circuit (IC), comprising:

• a control circuit defining a reset terminal and configured to determine an error condition in the IC and to generate a reset signal on the reset terminal, based on determining the error condition in the IC;
• a field-effect transistor (FET) defining a drain connected to an output terminal of the IC, and a source connected to a ground terminal of the IC, the FET configured to selectively conduct a first current between the output terminal and the ground terminal to drive the output terminal to a low voltage state, thereby signaling the error condition in the IC;
• an internal pull-up resistor connected between a signal terminal of the IC and a gate of the FET to conduct a second current therebetween and to drive the FET to a conductive state;
• and
• a FET driver circuit connected to the reset terminal of the control circuit and configured to selectively drive the FET to a non-conductive state in response to the reset signal;
• and
• an RO driver circuit, including:
• a second FET defining a drain connected to the output terminal of the IC, and a source connected to the ground terminal of the IC, and configured to selectively conduct a third current between the output terminal and the ground terminal of the IC;
• a voltage regulator configured to produce a filtered operating voltage on a common node using an operating power from an input terminal of the IC;
• a capacitor connected between the common node and the ground terminal to maintain the filtered operating voltage on the common node;
• and
• a third FET defining a drain connected to a gate of the second FET, and a source connected to the common node;
• wherein the third FET is configured to selectively conduct a fourth current between the common node and the gate of the second FET to drive the second FET to a conductive state, thereby conducting the third current between the output terminal and the ground terminal of the IC for a period of time after an ending of the reset signal, while the capacitor maintains the filtered operating voltage at a value sufficient to drive the second FET to a conductive state;
• and
• wherein the period of time is longer than a pull-up time for the second current to drive the FET from the non-conductive state to the conductive state.

A power supply circuit for a system in a vehicle, comprising:

• a power source having a power output terminal;
• a safety microcontroller unit (MCU) having a signal input terminal;
• and
• a power management integrated circuit (PMIC) including:
• a voltage input terminal, a ground terminal, a power output terminal, and a signal output terminal, wherein the voltage input terminal is connected to the power output terminal of the power source for receiving power therefrom, and wherein the signal output terminal is connected to the signal input terminal of the safety MCU for signaling an error condition in the PMIC;
• a control circuit defining a reset terminal and configured to determine the error condition in the PMIC and to generate a reset signal on the reset terminal based on determining the error condition in the PMIC;
• a field-effect transistor (FET) defining a drain connected to the signal output terminal, and a source connected to the ground terminal, the FET configured to selectively conduct a first current between the signal output terminal and the ground terminal to drive the signal output terminal to a low voltage state, thereby signaling the error condition in the PMIC;
• an internal pull-up resistor connected between the signal output terminal and a gate of the FET to conduct a second current therebetween and to drive the FET to a conductive state;
• and
• a FET driver circuit connected to the reset terminal of the control circuit and configured to selectively drive the FET to a non-conductive state in response to the reset signal.