Apparatuses and methods for adjusting skews between data and clock

An apparatus driven by a power voltage, the apparatus comprising:

• a data input circuit comprising a sampler circuit configured to receive a data signal and latch the data signal in response to a clock signal provided by a clock delay scheduler;
• and
• a clock circuit comprising:
• the clock delay scheduler;
• a clock buffer;
• a duty corrector;
• a first logic circuit;
• and a scheduler controller,
• wherein the clock circuit is configured to:
• receive, through the clock buffer, a first clock signal having a first swing width,
• convert the first clock signal into a second clock signal amplified to a second swing width greater than the first swing width, and
• adjust a skew between the data signal and the second clock signal,
• wherein a first loop comprises the clock delay scheduler, the duty corrector, the sampler circuit, and a first count logic circuit, and a second loop comprises the scheduler controller and the clock delay scheduler,
• wherein the duty corrector is configured to receive the first clock signal from the clock buffer and to adjust a duty cycle of the first clock signal based on a first count code,
• wherein the first count logic circuit is configured to receive the data signal from the sampler circuit and to generate the first count code based on a phase difference between the second clock signal and the data signal,
• wherein the clock delay scheduler is configured to receive the first clock signal from the duty corrector and adjust the first clock signal based on a second count code,
• wherein the scheduler controller is configured to generate the second count code based on a first adjustment code and a second adjustment code, and
• wherein the clock circuit is further configured to:
• obtain a first value of the first count code by causing one or more first loop operations to be performed through the first loop while a level of the power voltage is a first power voltage level, and store the first value as the first adjustment code,
• obtain a second value of the first count code by causing one or more of the one or more first loop operations to be performed through the first loop while the level of the power voltage is a second power voltage level higher than the first power voltage level, and store the second value as the second adjustment code, and
• based on identifying a difference between a first slope representing a change in a delay of the data signal with respect to the first power voltage level and the second power voltage level and a second slope representing a change in a delay of the clock signal, cause one or more second loop operations to be performed through the second loop until the first slope and the second are identical.

A method for adjusting a skew between a data signal and a clock signal of an apparatus driven by a power voltage and including a sampler circuit that latches the data signal in response to the clock signal, the method comprising:

• receiving the data signal through a data buffer of the apparatus;
• receiving the clock signal through a clock buffer of the apparatus;
• based on identifying a phase difference between the data signal and the clock signal, repeatedly performing one or more first loop operations through a first loop of the apparatus until the phase difference is eliminated, wherein the first loop includes the sampler circuit and a first count logic circuit;
• obtaining a first adjustment code by causing one or more of the one or more first loop operations to be performed through the first loop while a level of the power voltage is a first power voltage level;
• obtaining a second adjustment code by causing one or more of the one or more first loop operations to be performed while the level of the power voltage is a second power voltage level higher than the first power voltage level;
• storing the first adjustment code and the second adjustment code in a scheduler controller of the apparatus;
• and
• based on identifying a difference between a first slope representing a change in a delay of the data signal with respect to the first power voltage level and the second power voltage level and a second slope representing a change in a delay of the clock signal, performing one or more second loop operations through a second loop of the apparatus until the first slope and the second slope are identical, wherein the second loop includes the scheduler controller and a clock delay scheduler of the apparatus.