Digital low dropout regulator for generating output voltage dependent on DAC code signal
AssigneeRenesas Design (UK) Limited
InventorJulian Tyrrell
Life of this patent
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Abstract
A digital low dropout regulator (LDO) for receiving a reference voltage and generating an output voltage, the digital LDO being synchronized to a clock signal and comprising a first digital to analog converter configured to generate a first DAC code signal, the output voltage being dependent the first DAC code signal, trigger state transitions of the first DAC code signal between states, and for at least a portion of the state transitions of the first DAC code signal, trigger each subsequent state transition after more clock cycles of the clock signal than for the preceding state transition.
Claims17
A digital low dropout regulator (LDO) for receiving a reference voltage and generating an output voltage, the digital LDO being synchronized to a clock signal and comprising:
- a first digital to analog converter configured to:
- generate a first DAC code signal, the output voltage being dependent the first DAC code signal;
- trigger state transitions of the first DAC code signal between states, the state transitions comprising rising transitions and/or falling transitions;
- trigger a first rising transition after n clock cycles, where n is a positive integer, and trigger a second rising transition after the first rising transition and after m clock cycles, where m is an integer and greater than n;
- and/or
- trigger a first falling transition after p clock cycles, where p is a positive integer, and trigger a second falling transition after the first falling transition and after q clock cycles, where q is an integer and greater than p.
A method of generating an output voltage using a digital LDO comprising a first digital to analog converter and synchronized to a clock signal comprising:
- receiving a reference voltage at the digital LDO;
- generating a first DAC code signal using the first digital to analog converter;
- triggering state transitions of the first DAC code signal between states using the first digital to analog converter, the state transitions comprising rising transitions and/or falling transitions;
- triggering a first rising transition after n clock cycles, where n is a positive integer, and triggering a second rising transition after the first rising transition and after m clock cycles, where m is an integer and greater than n;
- and/or
- triggering a first falling transition after p clock cycles, where p is a positive integer, and triggering a second falling transition after the first falling transition and after q clock cycles, where q is an integer and greater than p;
- and nverter;
- and
- generating the output voltage, the output voltage being dependent on the first DAC code signal.
Dependencies are inferred from the claim text.