Semiconductor package and method of manufacturing the semiconductor package

A semiconductor package, comprising:

• first, second, third and fourth semiconductor chips sequentially stacked on one another,
• wherein each of the first, second and third semiconductor chips includes
• a first group of through electrodes and a second group of through electrodes alternately arranged in a first direction, and
• input/output (I/O) circuitry selectively connected to the first group of through electrodes respectively, such that only one in every four through electrodes in the first direction is operably connected to the I/O circuitry,
• wherein the first group of through electrodes of the first and third semiconductor chips are electrically connected to the second group of through electrodes of the second and fourth semiconductor chips respectively,
• wherein the second group of through electrodes of the first and third semiconductor chips are electrically connected to the first group of through electrodes of the first and third semiconductor chips respectively,
• wherein an I/O circuitry of the fourth semiconductor chip is configured to transmit a signal through the second group of through electrodes of the third semiconductor chip, the first group of through electrodes of the second semiconductor chip, and the second group of through electrodes of the first semiconductor chip, and
• wherein the second group of through electrodes of the third semiconductor chip is vertically aligned with the first group of through electrodes of the second semiconductor chip.

A semiconductor package, comprising:

• first, second, third and fourth semiconductor chips sequentially stacked on one another and electrically connected to each other by conductive connection members,
• wherein each of the first, second, third and fourth semiconductor chips includes
• a first surface and a second surface opposite to each other,
• a first group of bonding pads and a second group of bonding pads on the respective first surface alternately arranged in a first direction, and
• input/output (I/O) circuitry selectively connected to the first group of bonding pads respectively, such that only one in every four bonding pads in the first direction is operably connected to the I/O circuitry,
• wherein each of the first, second and third semiconductor chips further includes
• a first group of through electrodes electrically connected to the first group of bonding pads, and
• a second group of through electrodes electrically connected to the second group of bonding pads stacked on a package substrate,
• wherein the first group of bonding pads of the first and third semiconductor chips are electrically connected to the second group of bonding pads of the second and fourth semiconductor chips respectively,
• wherein the second group of bonding pads of the first and third semiconductor chips are electrically connected to the first group of bonding pads of the second and fourth semiconductor chips respectively,
• wherein the I/O circuitry of the fourth semiconductor chip is configured to transmit a signal through the second group of through electrodes of the third semiconductor chip, the first group of through electrodes of the second semiconductor chip, and the second group of through electrodes of the first semiconductor chip, and
• wherein the second group of through electrodes of the third semiconductor chip is vertically aligned with the first group of through electrodes of the second semiconductor chip.