Embedded flip chip package substrate and manufacturing method thereof

A manufacturing method for an embedded flip chip package substrate, the method comprising:

• providing a carrier plate;
• preparing a first line layer on an upper surface of the carrier plate;
• laminating a first dielectric layer on the first line layer;
• forming a first window on the first dielectric layer, and filling a first copper post in the first window so that the first copper post is electrically connected to the first line layer;
• forming a second window on the first dielectric layer, and installing a flip chip on the second window such that the first line layer and a terminal of the flip chip are electrically connected through the second window;
• sequentially stacking a packaging layer and a second dielectric layer on the first dielectric layer, wherein the second dielectric layer is covered with a first metal layer on the upper surface remote from the packaging layer;
• pressing the packaging layer and the second dielectric layer such that the packaging layer encapsulates the first copper post and the flip chip, and curing the packaging layer;
• opening a hole through the first metal layer, the second dielectric layer, and the packaging layer to form an interlayer conducting blind hole, wherein the interlayer conducting blind hole exposes the upper surface of the first copper post;
• forming a second line layer on the upper surface of the first metal layer, wherein the second line layer is electrically connected to the first line layer through the first copper post;
• and
• removing the carrier plate to obtain the package substrate.