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US 12,588,524 B2Granted
Stacked via modulator in high speed interconnect
AssigneeIntel Corporation
InventorsJiwei Sun, Zhiguo Qian, Kemal Aygün
Life of this patent
Estimating the term…
Abstract
Embodiments disclosed herein include electronic packages In an embodiment, the electronic package comprises first substrate layers, and a core under the first substrate layers. In an embodiment, second substrate layers are under the core, and an interconnect is through the first substrate layers, the core, and the second substrate layers. In an embodiment, a portion of the interconnect through the second substrate layers comprises a pad, and a plurality of vias extending away from the pad.
Claims19
An electronic package, comprising:
- first substrate layers;
- a core under the first substrate layers;
- second substrate layers under the core;
- and
- an interconnect through the first substrate layers, the core, and the second substrate layers, wherein a portion of the interconnect through the second substrate layers comprises:
- a pad, wherein the pad is square;
- and
- a plurality of vias extending away from the pad, wherein the plurality of vias comprises four vias, and wherein each via is proximate to a corner of the square pad;
- and
- wherein a portion of the interconnect through the core comprises a plated through hole having a maximum lateral width, wherein the pad of the portion of the interconnect through the second substrate layers has a lateral width greater than the maximum lateral width of the plated through hole.
7 more elements
An electronic package, comprising:
- first substrate layers;
- a core under the first substrate layers;
- second substrate layers under the core;
- and
- an interconnect through the first substrate layers, the core, and the second substrate layers, wherein a portion of the interconnect through the second substrate layers comprises:
- a pad;
- and
- a plurality of vias extending away from the pad;
- and
- wherein a portion of the interconnect through the core comprises a plated through hole having a maximum lateral width, wherein the pad of the portion of the interconnect through the second substrate layers has a lateral width greater than the maximum lateral width of the plated through hole, wherein the plurality of vias comprises at least six vias, and wherein the plurality of vias are laid out in a hexagon pattern.
7 more elements
An electronic package, comprising:
- first substrate layers;
- a core under the first substrate layers;
- second substrate layers under the core;
- and
- an interconnect through the first substrate layers, the core, and the second substrate layers, wherein a portion of the interconnect through the second substrate layers comprises:
- a pad;
- and
- a plurality of vias extending away from the pad;
- and
- wherein a portion of the interconnect through the core comprises a plated through hole having a maximum lateral width, wherein the pad of the portion of the interconnect through the second substrate layers has a lateral width greater than the maximum lateral width of the plated through hole, wherein the plurality of vias comprises at least eight vias, and wherein the plurality of vias are laid out in a circular pattern.
7 more elements
An electronic package, comprising:
- first substrate layers;
- a core under the first substrate layers;
- second substrate layers under the core;
- and
- an interconnect through the first substrate layers, the core, and the second substrate layers, wherein a portion of the interconnect through the second substrate layers comprises:
- a pad;
- and
- a stub that extends laterally out from the pad, wherein the stub comprises a patch that surrounds the pad;
- and
- wherein a portion of the interconnect through the core comprises a plated through hole having a maximum lateral width, wherein the pad of the portion of the interconnect through the second substrate layers has a lateral width greater than the maximum lateral width of the plated through hole.
7 more elements
An electronic package, comprising:
- first substrate layers;
- a core under the first substrate layers;
- second substrate layers under the core;
- and
- an interconnect through the first substrate layers, the core, and the second substrate layers, wherein a portion of the interconnect through the second substrate layers comprises:
- a pad;
- and
- a plurality of stubs that extend laterally out from the pad, wherein the plurality of stubs are rectangular stubs;
- and
- wherein a portion of the interconnect through the core comprises a plated through hole having a maximum lateral width, wherein the pad of the portion of the interconnect through the second substrate layers has a lateral width greater than the maximum lateral width of the plated through hole.
7 more elements
An electronic package, comprising:
- first substrate layers;
- a core under the first substrate layers;
- second substrate layers under the core;
- and
- an interconnect through the first substrate layers, the core, and the second substrate layers, wherein a portion of the interconnect through the second substrate layers comprises:
- a pad;
- and
- a plurality of stubs that extend laterally out from the pad;
- and
- a distal pad at an end of each of the plurality of stubs;
- and
- wherein a portion of the interconnect through the core comprises a plated through hole having a maximum lateral width, wherein the pad of the portion of the interconnect through the second substrate layers has a lateral width greater than the maximum lateral width of the plated through hole.
9 more elements
Dependencies are inferred from the claim text.