Generation of physically unclonable function using one-time-programmable memory devices with backside interconnect structures

A memory system, comprising:

• a memory array comprising a plurality of memory cells formed on a first side of a substrate, each of the plurality of memory cells presenting a logic state of either a first logic state or a second logic state and comprising:
• a programming transistor comprising a first source/drain terminal, a second source/drain terminal, and a gate terminal operatively connected to a programming word line that is configured to receive a programming voltage;
• a first reading transistor comprising a first source/drain terminal operatively coupled to the first source/drain terminal of the programming transistor, and a second source/drain terminal operatively coupled to a first bit line formed on a second side of the substrate opposite to the first side;
• and
• a second reading transistor comprising a first source/drain terminal coupled to the second source/drain terminal of the programming transistor, and a second source/drain terminal coupled to a second bit line formed on the second side of the substrate, the second bit line being different from the first bit line;
• and
• an authentication circuit operatively coupled to the memory array and configured to generate a bit of a Physically Unclonable Function (PUF) signature for each of the plurality of memory cells based on the logic state thereof.

A method for forming a memory device, comprising:

• providing a substrate;
• forming a memory cell on a first side of the substrate, comprising:
• forming, on the first side, a programming transistor having a first source/drain terminal, a second source/drain terminal, and a gate terminal operatively connected to a programming word line that is configured to receive a programming voltage;
• forming, on the first side, a first reading transistor having a first source/drain terminal coupled to the first source/drain terminal of the programming transistor;
• and
• forming, on the first side, a second reading transistor having a first source/drain terminal coupled to the second source/drain terminal of the programming transistor;
• forming a first bit line formed on a second side of the substrate opposite to the first side;
• and
• forming a second bit line formed on the second side of the substrate and different from the first bit line.