Stacked semiconductor method and apparatus

A chip package, comprising:

• one or more top dies;
• one or more bottom dies;
• a first interconnecting layer;
• a second interconnecting layer, wherein a first surface of each of the one or more top dies is coupled to the first interconnecting layer, wherein a first surface of each of the one or more bottom dies is coupled to the second interconnecting layer, wherein the first and second interconnecting layers each comprise:
• a layer comprising copper pads and a dielectric layer, wherein the first and second interconnecting layers between the one or more top dies and the one or more bottom dies are coupled via hybrid copper bonding;
• a material comprising silicon, wherein the material is deposited to at least partially cover the second interconnecting layer, wherein the one or more top dies and the material define a continuous surface;
• a support die, wherein a first surface of the support die is coupled to a second surface of the one or more top dies;
• and
• a plurality of microbumps, wherein the plurality of microbumps are coupled to a second surface of at least one of the one or more bottom dies, the one or more bottom dies comprising through-silicon vias exposed at the second surface, the microbumps coupled to the through-silicon vias and to an interposer.