Thermal and mechanical enhanced thermal module structure on heterogeneous packages and methods for forming the same

A chip package assembly, comprising:

• a package substrate;
• a fan-out package attached to the package substrate, the fan-out package comprising:
• a first semiconductor die including a first physical layer interface configured to transmit signals to, and from, the packaging substrate;
• a second semiconductor die including a second physical layer interface configured to transmit signals to, and from, the packaging substrate;
• and
• an underfill material portion laterally surrounding the first semiconductor die and the second semiconductor die;
• a heatsink structure including a heatsink base and a cavity within the heatsink base;
• a thermoelectric cooler (TEC) embedded within the cavity, wherein the TEC is positioned above the first physical layer interface and the second physical layer interface;
• and
• a fan-out package thermal interface material (TIM) layer directly contacting an entirety of a bottom surface of the TEC, an entirety of top surfaces of the first semiconductor die and the second semiconductor die, and a top surface of the underfill material portion, wherein:
• the TEC has an areal overlap with an entirety of the first physical layer interface of the first semiconductor die and with an entirety of the second physical layer interface of the second semiconductor die in a plan view along a vertical direction;
• the chip package assembly comprises a molding compound die frame that laterally surrounds the first semiconductor die, the second semiconductor die, and the underfill material portion;
• a portion of the first semiconductor die other than the first physical layer interface does not have any areal overlap with the TEC in the plan view;
• and
• a portion of the second semiconductor die other than the second physical layer interface does not have any areal overlap with the TEC in the plan view.

A method of forming a chip package assembly, comprising:

• attaching a fan-out package to a package substrate, wherein the fan-out package comprises a first semiconductor die including a first physical layer interface configured to transmit signals to, and from, the packaging substrate, a second semiconductor die including a second physical layer interface configured to transmit signals to, and from, the packaging substrate, and an underfill material portion laterally surrounding the first semiconductor die and the second semiconductor die;
• and
• attaching a combination of a heatsink structure and a thermoelectric cooler (TEC) to the fan-out package, wherein the heat sink structure includes a heatsink base and a cavity within the heatsink base, and the TEC is embedded within the cavity, and wherein a fan-out package thermal interface material (TIM) layer is formed between the combination and the fan-out package such that the fan-out package TIM layer directly contacts an entirety of a bottom surface of the TEC, an entirety of top surfaces of the first semiconductor die and the second semiconductor die, and a top surface of the underfill material portion, wherein:
• the heatsink structure includes a heatsink base and a cavity within the heatsink base;
• a thermoelectric cooler (TEC) is embedded within the cavity, wherein the TEC is positioned above the first physical layer interface and the second physical layer interface;
• the TEC has an areal overlap with an entirety of the first physical layer interface of the first semiconductor die and with an entirety of the second physical layer interface of the second semiconductor die in a plan view along a vertical direction;
• a portion of the first semiconductor die other than the first physical layer interface does not have any areal overlap with the TEC in the plan view;
• and
• a portion of the second semiconductor die other than the second physical layer interface does not have any areal overlap with the TEC in the plan view.