Die stitching and harvesting of arrayed structures
AssigneeApple Inc.
InventorsSanjay Dabral, Jun Zhai, Kunzhong Hu, Raymundo M. Camenforte
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Abstract
Multi-die structures with die-to-die routing are described. In an embodiment, each die is patterned into the same semiconductor substrate, and the dies may be interconnected with die-to-die routing during back-end wafer processing. Partial metallic seals may be formed to accommodate the die-to-die routing, programmable dicing, and various combinations of full metallic seals and partial metallic seals can be formed. This may also be extended to three dimensional structures formed using wafer-on-wafer or chip-on-wafer techniques.
Claims19
A chip structure comprising:
- a semiconductor substrate;
- a first front-end-of-the line (FEOL) die area of a first die patterned into the semiconductor substrate, the first FEOL die area including a first device area and a first input/output region;
- a back-end-of-the-line (BEOL) build-up structure spanning over the first device area and the first input/output region;
- a scribed chip edge adjacent to the first input/output region;
- wherein the BEOL build-up structure comprises a die-to-die routing connected between the first input/output region and a terminal end of the die-to-die routing at the scribed chip edge;
- wherein the semiconductor substrate, the first FEOL die area, and BEOL build-up structure form a first die level;
- and
- a second die level hybrid bonded to the first die level, the second die level including a second FEOL die area of a second die patterned into a second semiconductor substrate.
A chip structure comprising:
- a semiconductor substrate;
- a first front-end-of-the line (FEOL) die area of a first die patterned into the semiconductor substrate, the first FEOL die area including a first device area and a first input/output region;
- a back-end-of-the-line (BEOL) build-up structure spanning over the first device area and the first input/output region;
- a scribed chip edge adjacent to the first input/output region;
- wherein the BEOL build-up structure comprises a die-to-die routing connected between the first input/output region and a terminal end of the die-to-die routing at the scribed chip edge;
- a second chip hybrid bonded with the BEOL build-up structure;
- and
- an encapsulation material laterally surrounding the second chip on the BEOL build-up structure.
An electronic structure comprising:
- a routing layer;
- one or more dies on a top side of the routing layer;
- a plurality of conductive bumps on an underside of the routing layer;
- and
- a multi-component device that includes a plurality of co-located components formed in a same substrate, and a terminal side including a plurality of terminals bonded to the underside of the routing layer laterally adjacent to the plurality of conductive bumps, wherein the terminal side of the multi-component device has a non-rectangular area.
Dependencies are inferred from the claim text.