Method for fabricating multiple work function layers

A method for fabricating multiple work function layers, at least comprising:

• step 1:
• providing a substrate, forming n transistor gates from a first to an nth transistor gates on the substrate, wherein each of the n transistor gates comprises a different work function from each other, where n is a natural number greater than or equal to 3;
• forming notches in the first to the nth transistor gates;
• and forming an HK layer and a blocking layer sequentially on the HK layer in the notches;
• step 2:
• depositing a first work function layer on the blocking layer on the first to the nth transistor gates, removing the first work function layer from above the first to the (n−1)th transistor gates through a first process of photolithography and etching, wherein the first process reserves the first work function layer above the nth transistor gate;
• step 3:
• depositing a second work function layer on the blocking layer and on the first to the (n−1)th transistor gates and the first work function layer above the nth transistor gate, removing the second work function layer from above the first to the (n−2)th transistor gates through a second process of photolithography and etching, wherein the second process reserves the second work function layer above the (n−1)th and nth transistor gates, wherein a thickness of the second work function layer is less than a thickness of the first work function layer;
• step 4:
• depositing a third work function layer on the blocking layer, the first to the (n−2)th transistor gates and the second work function layer above the (n−1)th and the nth transistor gates, removing the third work function layer from above the first to (n−3)th transistor gates through a third process of photolithography and etching, wherein the third process reserves the third work function layer above the (n−2)th, (n−1)th and nth transistor gates, wherein a thickness of the third work function layer is less than the thickness of the second work function layer;
• step 5:
• in a case that there are more than 4 transistor gates, wherein each of which has a different work function from each other, depositing a third to (n−1)th work function layers sequentially by analogy according to step 2 to step 4 until only the blocking layer exists on a last transistor gate, wherein thicknesses of the deposited third to the (n−1)th work function layers decrease sequentially and gradually;
• and
• step 6:
• sequentially forming a TiAlC layer, a TiN layer, and a back-end metal connecting hole from bottom to top.