US 12,588,437 B2 · Integrated dipole region for transistor

Abstract

Methods of manufacturing and processing semiconductor devices (i.e., electronic devices) are described. Embodiments of the disclosure advantageously provide electronic devices which meet reduced thickness, lower thermal budget, and Vt requirements, and have improved device performance and reliability. The electronic devices described herein comprise a source region, a drain region, and a channel separating the source region and the drain region, an interfacial layer on a top surface of the channel, a high-κ dielectric layer on the interfacial layer, a dipole layer on the high-κ dielectric layer, and a capping layer on the dipole layer. In some embodiments, the dipole layer comprises a metal oxynitride (MON), such as aluminum oxynitride (AlON). In some embodiments, the methods comprise annealing the substrate to drive atoms from the dipole layer into one or more of the interfacial layer or the high-k dielectric layer.

Claims14

Dependent claims

A method of manufacturing an electronic device, the method comprising:

depositing an interfacial layer on a top surface of a channel located between a source and a drain on a semiconductor substrate;
depositing a high-κ dielectric layer on the interfacial layer;
exposing the semiconductor substrate to a co-flow of a metal-containing precursor and a nitrogen-containing reactant, a pulse of the metal-containing precursor, and a pulse an oxygen-containing reactant to deposit a dipole layer on the high-κ dielectric layer, the dipole layer comprising a metal oxynitride (MON);
and
depositing a capping layer on the dipole layer.

2 more elements

Dependencies are inferred from the claim text.

Integrated dipole region for transistor

Life of this patent

Integrated dipole region for transistor

Life of this patent

Abstract

Claims14