Structure and method for memory element to confine metal with spacer

A method comprising:

• forming a memory element over a first portion of an insulator layer, wherein a portion of the memory element includes a sidewall over the insulator layer and forming the memory element includes:
• forming a lower electrode of the memory element, and
• forming an upper electrode of the memory element on the lower electrode;
• forming a metal-dielectric layer on the insulator layer and the memory element, wherein the upper electrode is above the metal-dielectric layer;
• and
• forming a spacer adjacent the sidewall of the memory element and on the first portion of the insulator layer,
• wherein forming the spacer confines the metal-dielectric layer within one of an interface between the spacer and the sidewall and an interface between the spacer and the first portion of the insulator layer, and the insulator layer includes a second portion free of the memory element, the spacer, and the metal-dielectric layer thereon.

A structure comprising:

• a memory element over a first portion of an insulator layer, wherein a portion of the memory element includes a sidewall over the insulator layer;
• a spacer including a hard masking material, adjacent the sidewall of the memory element and on the first portion of the insulator layer;
• and
• a metal-dielectric layer within one of an interface between the spacer and the sidewall and an interface between the spacer and the first portion of the insulator layer,
• wherein the insulator layer includes a second portion adjacent the first portion, and the second portion does not include the memory element, the spacer, and the metal-dielectric layer thereon.