Memory element with a hardmask stack having different stress levels
AssigneeInternational Business Machines Corporation
InventorsOscar van der Straten, Lisamarie White, Willie Lester Muchrison, Jr., Scott A. DeVries, Daniel Charles Edelstein, Michael Rizzolo, Chih-Chao Yang
Life of this patent
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Abstract
Embodiments of the invention are directed to an integrated circuit (IC) structure that includes a memory element a non-sacrificial hardmask stack over the memory element. The non-sacrificial hardmask stack includes a first hardmask region and a second hardmask region. A compressive stress level of the first hardmask region is greater than a compressive stress level of the second hardmask region.
Claims20
An integrated circuit (IC) structure comprising:
- a memory element;
- and
- a non-sacrificial hardmask stack over the memory element;
- wherein the non-sacrificial hardmask stack exhibits an overall compressive stress;
- wherein the non-sacrificial hardmask stack comprises a first hardmask region and a second hardmask region;
- wherein the first hardmask region exhibits a first compressive stress, and the second hardmask region exhibits a second compressive stress;
- and
- wherein a level of the overall compressive stress is based at least in part on a level of the first compressive stress being greater than a level of the second compressive stress.
An integrated circuit (IC) structure comprising:
- a memory element;
- and
- a non-sacrificial hardmask stack over the memory element;
- wherein the non-sacrificial hardmask stack exhibits an overall compressive stress;
- wherein the non-sacrificial hardmask stack comprises a plurality of first hardmask regions and a plurality of second hardmask regions;
- wherein each of the plurality of first hardmask regions is adjacent to one of the plurality of second hardmask regions;
- wherein each of the plurality of first hardmask regions exhibits a first compressive stress, and each of the plurality of second hardmask regions exhibits a second compressive stress;
- and
- wherein a level of the overall compressive stress is based at least in part on a level of the first compressive stress being greater than a level of the second compressive stress.
A method of forming a portion of an integrated circuit (IC) structure, the method comprising:
- forming a memory element;
- and
- forming a non-sacrificial hardmask stack over the memory element;
- wherein the non-sacrificial hardmask stack exhibits an overall compressive stress;
- wherein the non-sacrificial hardmask stack comprises a first hardmask region and a second hardmask region;
- wherein the first hardmask region exhibits a first compressive stress, and the second hardmask region exhibits a second compressive stress;
- and
- wherein a level of the overall compressive stress is based at least in part on a level of the first compressive stress being greater than a level of the second compressive stress.
Dependencies are inferred from the claim text.