Image sensor including a buried gate

An image sensor, comprising:

• a stack structure including a first substrate and a second substrate that is stacked upon the first substrate, an active pixel region in which a plurality of pixels is defined, and a pad region disposed on at least one side of the active pixel region,
• wherein the first substrate comprises:
• a first semiconductor substrate including a first surface and a second surface, the first semiconductor substrate having a photoelectric conversion region disposed therein;
• a first buried gate electrode having at least a part extending from the first surface of the first semiconductor substrate towards an interior of the first semiconductor substrate, the first buried gate electrode having a semi-annular horizontal cross-section;
• a second buried gate electrode having at least a part extending from the first surface of the first semiconductor substrate towards an interior of the first semiconductor substrate, the second buried gate electrode being spaced apart from the first buried gate electrode, the second buried gate electrode having a semi-annular horizontal cross-section;
• a floating diffusion region disposed within the first semiconductor substrate and at least partially surrounded by the first buried gate electrode and the second buried gate electrode;
• a first conductive via extending from the first buried gate electrode to connect to a first pattern of one wiring layer;
• a second conductive via extending from the second buried gate electrode to connect to a second pattern of the one wiring layer;
• and
• a third conductive via extending from the floating diffusion region to connect to a third pattern of the one wiring layer.

An image sensor, comprising:

• a stack structure including a first substrate and a second substrate that is stacked on the first substrate, an active pixel region in which a plurality of pixels is defined, and a pad region disposed on at least one side of the active pixel region,
• wherein the first substrate comprises:
• a first semiconductor substrate including a first surface and a second surface, the first semiconductor substrate having a photoelectric conversion region disposed therein;
• a floating diffusion region disposed within the first semiconductor substrate, the floating diffusion region being adjacent to the first surface;
• a first buried gate electrode disposed within a first buried gate trench that is recessed with respect to the first surface, the first buried gate trench extending from the first surface of the first semiconductor substrate towards an interior of the first semiconductor substrate, and on a first side part of the floating diffusion region, the first buried gate electrode having a semi-annular horizontal cross-section;
• a second buried gate electrode disposed within a second buried gate trench that is recessed with respect to the first surface, the second buried gate trench extending from the first surface of the first semiconductor substrate towards the interior of the first semiconductor substrate and spaced apart from the first buried gate trench, and on a second side part of the floating diffusion region, the second side part being opposite to the first side part, the second buried gate electrode having a semi-annular horizontal cross-section;
• a first conductive via extending from the first buried gate electrode to connect to a first pattern of one wiring layer;
• a second conductive via extending from the second buried gate electrode to connect to a second pattern of the one wiring layer;
• and
• a third conductive via extending from the floating diffusion region to connect to a third pattern of the one wiring layer,
• wherein each of the first buried gate electrode and the second buried gate electrode at least partially surround the floating diffusion region, and the second substrate comprises a logic circuit configured to drive the plurality of pixels.