Capacitor and method for forming the same

An integrated circuit (IC) structure, comprising:

• a substrate having an active region;
• a dielectric material embedded in the substrate and laterally surrounding the active region;
• a gate strip over the active region;
• and
• a capacitor over the dielectric material, wherein the capacitor comprises:
• a first dummy gate strip at a same level height as the gate strip, and wherein no conductive connections exist between the first dummy gate strip and the gate strip at a height of the first dummy gate strip and the gate strip;
• a second dummy gate strip extending in parallel with the first dummy gate strip;
• a first stack of metal strips directly above the first dummy gate strip;
• and
• a second sack of metal strips directly above the second dummy gate strip, wherein the first stack of metal strips is electrically connected to the second stack of metal strips only at a topmost level of the first and second stacks of metal strips without electrical connection at other levels of the first and second stacks of metal strips.

A method for forming an integrated circuit (IC) structure, comprising:

• forming a shallow trench isolation (STI) in a substrate to define an active region in the substrate;
• forming a metal gate over the active region, a first dummy gate over the STI, and a second dummy gate over the STI;
• forming a gate contact over the metal gate, a plurality of first metal contacts over the first dummy gate, and a plurality of second metal contacts over the second dummy gate;
• forming a first stack of metal strips directly above the first metal contacts and a second stack of metal strips directly above the second metal contacts, the metal strips in the first stack extending in a same direction as a lengthwise direction of the first dummy gate, wherein the first stack of metal strips is electrically connected to the second stack of metal strips only at a topmost level of the first and second stacks of metal strips without electrical connection at other levels of the first and second stacks of metal strips;
• and
• forming a dielectric layer laterally surrounding the first dummy gate, wherein the first dummy gate has opposing ends in the lengthwise direction of the first dummy gate that are in contact with the dielectric layer.