An active device substrate, comprising:
- a first conductive layer located above a substrate, wherein the first conductive layer comprises a transfer wire and a first bottom gate, and the transfer wire is physically separated from the first bottom gate;
- a first insulating layer, located above the first conductive layer;
- a second insulating layer, located above the first insulating layer;
- a first semiconductor pattern and a second semiconductor pattern, located between the first insulating layer and the second insulating layer;
- a first connection structure and a second connection structure, located above the second insulating layer and respectively filled into a first via and a second via that run through the first insulating layer and the second insulating layer to electrically connect to the transfer wire, wherein the first semiconductor pattern, the first connection structure, the transfer wire, the second connection structure, and the second semiconductor pattern are connected in sequence;
- a first gate and a second gate, respectively overlapping the first semiconductor pattern and the second semiconductor pattern, wherein the first semiconductor pattern is located between the first bottom gate and the first gate, the first semiconductor pattern is physically connected to the first connection structure, the first connection structure is physically connected to the transfer wire, the transfer wire is physically connected to the second connection structure, and the second connection structure is physically connected to the second semiconductor pattern;
- a third insulating layer, located on the first connection structure, the second connection structure, and the second insulating layer;
- a first source/drain and a second source/drain, located above the third insulating layer and electrically connected to the first semiconductor pattern and the second semiconductor pattern, respectively;
- further comprises:
- a second conductive layer, located between the second insulating layer and the third insulating layer and comprising the first gate and the second gate;
- a fourth insulating layer, located above the third insulating layer;
- a third conductive layer, located between the third insulating layer and the fourth insulating layer and comprising a capacitive electrode, the first connection structure, and the second connection structure, wherein the capacitive electrode overlaps the first gate;
- and
- a fourth conductive layer, located above the fourth insulating layer and comprising the first source/drain and the second source/drain;
- a third semiconductor pattern, located between the first insulating layer and the second insulating layer;
- wherein the second conductive layer further comprises:
- a scanning line and a signal line, extending along a first direction, wherein the signal line partially overlaps the transfer wire and is located between the first connection structure and the second connection structure;
- and
- a third gate, electrically connected to the scanning line and overlapping the third semiconductor pattern;
- wherein the fourth conductive layer further comprises:
- a data line, extending along a second direction and electrically connected to the third semiconductor pattern.