Stacked electronic devices having independent gates
AssigneeInternational Business Machines Corporation
InventorsMin Gyu Sung, Ruilong Xie, Julien Frougier, Chanro Park, Juntao Li
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Abstract
Embodiments of the invention are directed to an integrated circuit (IC) that includes a stacked device configuration having a top electronic device positioned over a bottom electronic device, along with an isolation region operable to electrically isolate at least a gate region of the top electronic device from a gate region of the bottom electronic device. The gate region of the top electronic device includes a first conductive material, and the gate region of the bottom electronic device includes a second conductive material that is different from the first conductive material.
Claims20
An integrated circuit (IC) comprising:
- a stacked device configuration comprising a top electronic device positioned over a bottom electronic device;
- an isolation region between the top electronic device and the bottom electronic device;
- and
- a first gate contact structure electrically coupled to a gate region of the top electronic device;
- wherein a bottom surface of the first gate contact structure is on a portion of the isolation region;
- wherein the gate region of the top electronic device comprises a top gate dielectric layer;
- and
- wherein the first gate contact structure extends through the top gate dielectric layer to allow the bottom surface of the first gate contact structure to be on the portion of the isolation region.
A method of fabricating an integrated circuit (IC), the method comprising:
- forming a stacked device configuration comprising a top electronic device positioned over a bottom electronic device;
- forming an isolation region between the top electronic device and the bottom electronic device;
- and
- forming a first gate contact structure electrically coupled to a gate region of the top electronic device;
- wherein a bottom surface of the first gate contact structure is on a portion of the isolation region;
- wherein the gate region of the top electronic device comprises a top gate dielectric layer;
- and
- wherein the first gate contact structure extends through the top gate dielectric layer to allow the bottom surface of the first gate contact structure to be on the portion of the isolation region.
Dependencies are inferred from the claim text.